參數(shù)資料
型號(hào): MC145152P2
廠商: MOTOROLA INC
元件分類: XO, clock
英文描述: CAP .22F 5.5V GOLD SD VERTICAL
中文描述: PLL FREQUENCY SYNTHESIZER, 22 MHz, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 26/36頁
文件大?。?/td> 718K
代理商: MC145152P2
MC145151–2 through MC145158–2
26
MOTOROLA
TIMING REQUIREMENTS
(Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
VDD
V
Guaranteed Limit
25
°
C
Guaranteed Limit
– 40 to 85
°
C
Unit
fclk
Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Refer to CLK tw(H) below
(Figure 6)
3
5
9
dc to 5.0
dc to 7.1
dc to 10
dc to 3.5
dc to 7.1
dc to 10
MHz
tsu
Minimum Setup Time, Data to CLK
(Figure 7)
3
5
9
30
20
18
30
20
18
ns
th
Minimum Hold Time, CLK to Data
(Figure 7)
3
5
9
40
20
15
40
20
15
ns
tsu
Minimum Setup Time, CLK to ENB
(Figure 7)
3
5
9
70
32
25
70
32
25
ns
trec
Minimum Recovery Time, ENB to CLK
(Figure 7)
3
5
9
5
10
20
5
10
20
ns
tw(H)
Minimum Pulse Width, CLK and ENB
(Figure 6)
3
5
9
50
35
25
70
35
25
ns
tr, tf
Maximum Input Rise and Fall Times — Any Input
(Figure 8)
3
5
9
5
4
2
5
4
2
μ
s
SWITCHING WAVEFORMS
Figure 6.
Figure 7.
VSS
— VDD
50%
50%
LAST
CLK
tsu
PREVIOUS
DATA
LATCHED
FIRST
CLK
ENB
CLK
DATA
50%
— VDD
VSS
— VDD
VSS
— VDD
VSS
tsu
trec
th
50%
CLK,
ENB
tw(H)
— VDD
VSS
4 fclk
1
*
*Assumes 25% Duty Cycle.
tt
90%
10%
tf
ANY
OUTPUT
Figure 8.
相關(guān)PDF資料
PDF描述
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