參數(shù)資料
型號(hào)： MC145152P2
廠商： MOTOROLA INC
元件分類： XO, clock
英文描述： CAP .22F 5.5V GOLD SD VERTICAL
中文描述： PLL FREQUENCY SYNTHESIZER, 22 MHz, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 23/36頁
文件大?。?/td> 718K
代理商： MC145152P2
MC145151–2 through MC145158–2
MOTOROLA
23
MC14515X–2 FAMILY CHARACTERISTICS AND DESCRIPTIONS
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage
– 0.5 to + 10.0
V
Input or Output Voltage (DC or Transient)
except SW1, SW2
– 0.5 to VDD + 0.5
V
Vout
Output Voltage (DC or Transient),
SW1, SW2 (Rpull–up = 4.7 k
)
– 0.5 to + 15
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
±
10
mA
IDD, ISS
PD
Tstg
TL
Supply Current, VDD or VSS Pins
Power Dissipation, per Package
±
30
mA
500
mW
Storage Temperature
– 65 to + 150
°
C
Lead Temperature, 1 mm from Case for
10 seconds
260
°
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
Power Dissipation Temperature Derating:
Plastic DIP: – 12 mW/
°
C from 65 to 85
°
C
SOG Package: – 7 mW/
°
C from 65 to 85
°
C
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Symbol
Parameter
Test Condition
V
– 40
°
C
25
°
C
85
°
C
Unit
VDD
Min
Max
Min
Max
Min
Max
VDD
Power Supply Voltage
Range
—
3
9
3
9
3
9
V
Iss
Dynamic Supply Current
fin = OSCin = 10 MHz,
1 V p–p ac coupled sine
wave
R = 128, A = 32, N = 128
3
5
9
—
—
—
3.5
10
30
—
—
—
3
7.5
24
—
—
—
3
7.5
24
mA
ISS
Quiescent Supply Current
(not including pull–up
current component)
Vin = VDD or VSS
Iout = 0
μ
A
3
5
9
—
—
—
800
1200
1600
—
—
—
800
1200
1600
—
—
—
1600
2400
3200
μ
A
Vin
VIL
Input Voltage — fin, OSCin
Low–Level Input Voltage
— fin, OSCin
Input ac coupled sine wave
—
500
—
500
—
500
—
mV p–p
Vout
≥
2.1 V
Vout
≥
3.5 V
Vout
≥
6.3 V
Vout
≤
0.9 V
Vout
≤
1.5 V
Vout
≤
2.7 V
Input dc
coupled
square wave
3
5
9
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
V
VIH
High–Level Input Voltage
— fin, OSCin
Input dc
coupled
square wave
3
5
9
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
V
VIL
Low–Level Input Voltage
— except fin, OSCin
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
VIH
High–Level Input Voltage
— except fin, OSCin
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
V
Iin
IIL
Input Current (fin, OSCin)
Input Leakage Current
(Data, CLK, ENB —
without pull–ups)
Vin = VDD or VSS
Vin = VSS
9
±
2
±
50
±
2
±
25
±
2
±
22
μ
A
9
—
– 0.3
—
– 0.1
—
– 1.0
μ
A
IIH
Input Leakage Current (all
inputs except fin, OSCin)
Vin = VDD
9
—
0.3
—
0.1
—
1.0
μ
A
(continued)
These devices contain protection circuitry to
protect against damage due to high static
voltages or electric fields. However, precau-
tions must be taken to avoid applications of any
voltage higher than maximum rated voltages
to these high–impedance circuits. For proper
operation, Vin and Vout should be constrained
to the range VSS
≤
(Vin or Vout)
≤
VDD
except for SW1 and SW2.
SW1 and SW2 can be tied through external
resistors to voltages as high as 15 V, indepen-
dent of the supply voltage.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD), except for inputs with pull–up devices.
Unused outputs must be left open.
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