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參數資料
| 型號： | MC141543 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Advanced Monitor On-Screen Display |
| 中文描述： | 先進的顯示器屏幕顯示 |
| 文件頁數： | 8/14頁 |
| 文件大?。?/td> | 469K |
| 代理商： | MC141543 |
MC141543
8
MOTOROLA
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 3 with two extra color
selections, making a total of four selections for that row.
Bit 0 PWMCK_EN — When this bit is set to 1, the HTONE/
PWMCK pin will be switched to a clock output which is syn-
chronous to the H sync and used as an external PWM (pulse
width modulation) clock source. Refer to the pin description
of HTONE/PWMCK for more information. After power–on,
the default value is 0.
Row 15 Coln 8
MSB
LSB
COLN 8
ROW 15
Bit 2–0 R, G and B — These bits control the color of Win-
dow 3. Window 1 occupies Columns 0–2 of Row 15; Window
2 occupies Columns 3–5; and Window 3 occupies 6–8. Win-
dow 1 has the highest priority, and Window 3 the least. If win-
dow overlapping occurs, the higher priority window will cover
the lower one, and the higher priority color will take over on
the overlap window area. If the start address is greater than
the end address, this window will not be displayed.
Frame Control Registers
Frame Control Register Row 15 Coln 9
LSB
COLN 9
MSB
Bit 7–0 VERTD — These eight bits define the vertical start-
ing position. There are a total of 256 steps, with an increment
of four horizontal lines per step for each field. The value can-
not be zero anytime, and the default value is 4.
Frame Control Register Row 15 Coln 10
Bit 6–0 HORD — These bits define the horizontal starting
position for character display. Seven bits give a total of 128
steps and each increment represents a five–dot shift to the
right on the monitor screen. The value cannot be zero any-
time, the default value is 15.
0
1
2
3
4
5
6
7
LSB
COLN 10
MSB
HORD
Frame Control Register Row 15 Coln 11
7
COLN 11
6
5
4
3
2
1
0
CH5 CH4
CH3
CH2
CH1
CH0
Bit 5–0 CH5–CH0 — These six bits determine the dis-
played character height. It is possible to have a proper char-
acter height by setting a value greater than or equal to 16 on
a different horizontal frequency monitor. Setting a value be-
low 16 will not have a predictable result. Figure 6 illustrates
how this chip expands the built–in character font to the de-
sired height.
Frame Control Register Row 15 Coln 12
Bit 7 OSD_EN — The OSD circuit is activated when this bit
is set.
Bit 6 BSEN — This bit enables the character bordering or
shadowing function when it is set.
Bit 5 SHADOW — Characters with black–edge shadowing
are selected if this bit is set; otherwise bordering prevails.
Bit 4 X64, Bit 3 X32B — This bit determines the number of
dots per horizontal line. There are 320 dots per horizontal
line if Bit X32B is clear, which is also the default power–on
state. Otherwise, 480 dots per horizontal sync line is chosen
when Bit X64 is clear, and 640 dots per horizontal sync line
when Bit X64 is set to 1. Refer to Table 2 for details.
Bit 0 FBKGC — Bit 0 determines the configuration of the
FBKG output pin. When it is clear, the FBKG pin outputs high
while displaying characters or windows; otherwise, the
FBKG pin outputs high only while displaying characters.
7
OSD_EN
COLN 12
6
5
4
3
2
1
0
BSEN SHADOW
FBKGC
X32B
X64
Table 2. Resolution Setting
Dots / Line
(X64, X32B)
( 0 , 0 )
( 1 , 0 )
( 0 , 1 )
( 1 , 1 )
320
320
480
640
Resolution
CGA
CGA
EGA
VGA
when CH=25
Built–in font
(10x16 matrix)
0
2
14
15
13
12
11
10
9
8
7
6
5
4
3
1
when CH=34
Display character
when CH=22
16 lines
22 lines
34 lines
25 lines
Figure 6. Variable Character Height
An IBM PC program called “AMOSD Font Editor” was writ-
ten for MC141543 editing purposes. This program generates
a set of S–Record or Binary record for the desired display
patterns to be masked onto the character ROM of the
MC141543.
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