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參數(shù)資料
| 型號： | MC12429 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High Frequency PLL Clock Generator(高頻PLL時鐘發(fā)生器) |
| 中文描述： | 高頻PLL時鐘發(fā)生器（高頻鎖相環(huán)時鐘發(fā)生器） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 93K |
| 代理商： | MC12429 |
MC12429
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
Figure 4. Serial Test Clock Block Diagram
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N DIVIDE
(2, 4, 8, 16)
0
1
PLL 12429
LATCH
Reset
PLOADB
MCOUNTER
SLOAD
T0
T1
T2
VCO_CLK
SHIFT
REG
14–BIT
DECODE
SDATA
SCLOCK
MCNT
FREF
SEL_CLK
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
DC CHARACTERISTICS
(TA = 0
°
to 70
°
C, VCC = 3.3V to 5.0V
±
5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
V
VCC = 3.3 to 5.0V
VIL
Input LOW Voltage
0.8
V
VCC = 3.3 to 5.0V
IIN
Input Current
1.0
mA
VOH
Output HIGH Voltage
TEST
2.5
V
IOH = –0.8mA
VOL
Output LOW Voltage
TEST
0.4
V
IOL = 0.8mA
VOH
Output HIGH Voltage
FOUT
FOUT
2.17
2.50
V
VCC0 = 3.3V (Notes 1., 2.)
VOL
Output LOW Voltage
FOUT
FOUT
1.41
1.76
V
VCC0 = 3.3V (Notes 1., 2.)
ICC
Power Supply Current
VCC
PLL_VCC
85
15
100
20
mA
1. Output levels will vary 1:1 with VCC0 variation.
2. 50
to VCC – 2.0V pulldown.
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