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參數(shù)資料
| 型號： | MC12429 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High Frequency PLL Clock Generator(高頻PLL時鐘發(fā)生器) |
| 中文描述： | 高頻PLL時鐘發(fā)生器（高頻鎖相環(huán)時鐘發(fā)生器） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 93K |
| 代理商： | MC12429 |
MC12429
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA
9–BIT
SR
2–BIT
SR
3–BIT SR
DIV 8
Figure 2. MC12429 Block Diagram
16MHz
S_LOAD
P_LOAD
S_DATA
S_CLOCK
XTAL1
XTAL2
OSC
4
5
PHASE
DETECTOR
28
7
9–BIT DIV M
COUNTER
LATCH
VCO
DIV N
(2, 4, 8, 16)
LATCH
400–800
MHz
FOUT
FOUT
+3.3 or 5.0V
25
24
23
VCC0
LATCH
TEST
20
+3.3 or 5.0V
PLL_VCC
2MHz
FREF
0
1
27
26
0
1
VCC1
21
+3.3 or 5.0V
M[8:0]
9
8 16
N[1:0]
2
17, 18
22, 19
OE
6
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:
FOUT = (FXTAL
÷
8) x M
÷
N
(1)
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200
≤
M
≤
400 for a 16MHz input reference.
Assuming that a 16MHz reference frequency is used the
above equation reduces to:
FOUT = 2 x M
÷
N
Substituting the four values for N (2, 4, 8, 16) yields:
FOUT = M, FOUT = M
÷
2,
FOUT = M
÷
4 and FOUT = M
÷
8
for 200 < M < 400
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 200 – 400MHz, 100 –
200MHz, 50 – 100MHz and 25 – 50MHz respectively. From
these ranges the user will establish the value of N required,
then the value of M can be calculated based on the
appropriate equation above. For example if an output
frequency of 131MHz was desired the following steps would
be taken to identify the appropriate M and N values. 131MHz
falls within the frequency range set by an N value of 4 so N
[1:0] = 01. For N = 4 FOUT = M
÷
2 and M = 2 x FOUT.
Therefore M = 131 x 2 = 262, so M[8:0] = 100000110.
Following this same procedure a user can generate any
whole frequency desired between 25 and 400MHz. Note that
for N > 2 fractional values of FOUT can be realized. The size
of the programmable frequency steps (and thus the indicator
of the fractional output frequencies acheivable) will be equal
to FXTAL
÷
8
÷
N.
For input reference frequencies other than 16MHz the set
of appropriate equations can be deduced from equation 1.
For computer applications another useful frequency base
would be 16.666MHz. From this reference one can generate
a family of output frequencies at multiples of the 33.333MHz
PCI clock. As an example to generate a 133.333MHz clock
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