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參數(shù)資料
| 型號(hào)： | MC12181D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 125 - 1000 MHZ FREQUENCY SYNTHESIZER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1000 MHz, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 110K |
| 代理商： | MC12181D |
MC12181
6
MOTOROLA RF/IF DEVICE DATA
It is important that the total external (to the IC) capacitance
seen by either OSCin or OSCout, be no greater than 30pF.
In operation, the crystal oscillator will start up with the
application of power. If the crystal is in a can that is not
grounded it is often possible to monitor the frequency of
oscillation by connecting an oscilloscope probe to the can;
this technique minimizes any disturbance to the circuit. If this
is not possible, a high impedance, low capacitance, FET
probe can be connected to either OSCin or OSCout. Signals
typically seen at those points will be very nearly sinusoidal
with amplitudes of roughly 300–600mVp–p. Some distortion
is inevitable and has little bearing on the accuracy of the
signal going to the phase detector.
Loop Filter Design
Because the device is designed for a non–frequency agile
synthesizer (i.e., how fast it tunes is not critical) the loop filter
design is very straight forward. The current output of the
charge pump allows the loop filter to be realized without the
need of any active components. The preferred topology for
the filter is illustrated in Figure 6.
Figure 6. Loop Filter
MC12181
Ph/Frq
Det
Chrg
Pump
Xtl
Osc
÷
25–40
Kp
N
Co
Ro
Ca
Rx
Cx
VCO
Kv
÷
8
÷
8
The Ro/Co components realize the primary loop filter. Ca is
added to the loop filter to provide for reference sideband
suppression. If additional suppression is needed, the Rx/Cx
realizes an additional filter. In most applications, this will not
be necessary. If all components are used, this results in a 4th
order PLL, which makes analysis difficult. To simplify this, the
loop design will be treated as a 2nd order loop (Ro/Co) and
additional guidelines are provided to minimize the influence
of the other components. If more rigorous analysis is needed,
mathematical/system simulation tools should be used.
Component
Guideline
Ca
Rx
Cx
<0.1
×
Co
>10
×
Ro
<0.1
×
Co
The focus of the design effort is to determine what the
loop’s natural frequency,
ω
o, should be. This is determined by
Ro, Co, Kp, Kv, and Nt. Because Kp, Kv, and Nt are given, it is
only necessary to calculate values for Ro and Co. There are
3 considerations in selecting the loop bandwidth:
1) Maximum loop bandwidth for minimum tuning speed
2) Optimum loop bandwidth for best phase noise
performance
3) Minimum loop bandwidth for greatest reference sideband
suppression
Usually a compromise is struck between these 3 cases,
however, for a fixed frequency application, minimizing the
tuning speed is not a critical parameter.
To specify the loop bandwidth for optimal phase noise
performance, an understanding of the sources of phase
noise in the system and the effect of the loop filter on them is
required. There are 3 major sources of phase noise in the
phase–locked loop – the crystal reference, the VCO, and the
loop contribution. The loop filter acts as a low–pass filter to
the crystal reference and the loop contribution. The loop filter
acts as a high–pass filter to the VCO with an in–band gain
equal to unity. The loop contribution includes the PLL IC, as
well as noise in the system; supply noise, switching noise,
etc. For this example, a loop contribution of 15dB has been
selected, which corresponds to data in Figure NO TAG.
The crystal reference and the VCO are characterized as
high–order 1/f noise sources. Graphical analysis is used to
determine the optimum loop bandwidth. It is necessary to
have noise plots from the manufacturers of both devices.
This method provides a straightforward approximation
suitable for quickly estimating the optimal bandwidth. The
loop contribution is characterized as white–noise or
low–order 1/f noise given in the form of a noise factor which
combines all the noise effects into a single value. The phase
noise of the Crystal Reference is increased by the noise
factor of the PLL IC and related circuitry. It is further
increased by the total divide–by–N ratio of the loop. This is
illustrated in Figure 7.
The point at which the VCO phase noise crosses the
amplified phase noise of the Crystal Reference is the point of
the optimum loop bandwidth. In the example of Figure 7, the
optimum bandwidth is approximately 15 KHz.
Figure 7. Graphical Analysis of Optimum Bandwidth
Closed Loop Response
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
Crystal Reference
15dB NF of the Noise
Contribution from Loop
20*log(Nt)
VCO
Optimum Bandwidth
10
100
1k
10k
100k
1M
Hz
d
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