參數(shù)資料
型號： MC10H181P
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 4-Bit Arithmetic Logic Unit/Function Generator
中文描述： 10H SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDIP24
封裝： PLASTIC, DIP-24
文件頁數(shù)： 3/5頁
文件大?。?/td> 158K
代理商： MC10H181P
MC10H181
2–277
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5.0%) (See Note)
0
°
+25
°
+75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
Input Current High
Pin 22
Pins 14,23
Pins 13,15,17
Pins 10,16,18,21
Pins 9,11,19,20
Input Current Low
Pins 9–11, 13–22
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
IE
IinH
—
159
—
145
—
159
mA
μ
A
—
—
—
—
—
0.5
720
405
515
475
465
—
—
—
—
—
—
0.5
450
255
320
300
275
—
—
—
—
—
—
0.3
450
255
320
300
275
—
IinL
μ
A
VOH
VOL
VIH
VIL
–1.02
–1.95
–1.17
–1.95
–0.84
–1.63
–0.84
–1.48
–0.98
–1.95
–1.13
–1.95
–0.81
–1.63
–0.81
–1.48
–0.92
–1.95
–1.07
–1.95
–0.735
–1.60
–0.735
–1.45
Vdc
Vdc
Vdc
Vdc
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket
or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
AC PARAMETERS
AC Switching Characteristics
0
°
C
+25
°
C
+75
°
C
Characteristic
Symbol
Input
Output
Conditions
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
Rise Time, Fall Time
Propagation Delay
t+ +, t– –
t+, t–
t+ +, t+ –,
t– +, t– –
t+, t–
t+ +, t+ –,
t– +, t– –
t+, t–
t+ +, t– –
t+, t–
t+ +, t– –
t+, t–
t+ –, t– +
t+, t–
t+ +, t– +
t+, t–
t+ +, t– –
t+, t–
t+ +, t– –
t+, t–
t+ –, t– +
t+, t–
t+ +, t+ –
t+, t–
t+ –, t– +
t+, t–
t– +, t+ –
t+, t–
t+ –, t– +
t+, t–
t+ –, t– +
t+, t–
Cn
Cn
Cn
Cn
Cn
A1
A1
A1
A1
A1
A1
A1
A1
A1
B1
B1
B1
B1
B1
B1
B1
B1
M
M
S1
S1
S1
S1
S1
S1
S1
S1
Cn+4
Cn+4
F1
F1
F1
F1
F1
F1
PG
PG
GG
GG
Cn+4
Cn+4
F1
F
PG
PG
GG
GG
Cn+4
Cn+4
F1
F1
F1
F1
PG
PG
Cn+4
Cn+4
GG
GG
A0,A1,A2,A3
A0,A1,A2,A3
A0
0.7
0.6
2.0
2.0
0.7
0.6
2.0
2.0
0.7
0.7
2.2
2.2
ns
ns
ns
Rise Time, Fall Time
Propagation Delay
1.0
0.7
3.0
2.2
1.0
0.7
3.0
2.2
1.2
0.7
3.3
2.4
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall Time
1.5
0.7
1.5
0.9
1.5
0.7
1.5
0.5
2.0
0.7
1.5
0.7
1.5
0.7
2.0
0.5
1.5
0.8
1.5
0.7
1.5
0.7
1.5
0.7
1.3
0.5
3.7
2.0
3.7
2.4
3.7
2.2
3.6
2.0
4.5
2.3
3.8
2.2
3.7
2.2
4.0
2.0
4.2
2.3
4.5
2.0
4.0
2.0
4.1
2.2
4.5
3.2
1.5
0.7
1.5
0.9
1.5
0.7
1.5
0.5
2.0
0.7
1.5
0.7
1.5
0.7
2.0
0.5
1.5
0.8
1.5
0.7
1.5
0.7
1.5
0.7
1.3
0.5
3.7
2.0
3.7
2.4
3.7
2.2
3.6
2.0
4.5
2.3
3.8
2.2
3.7
2.2
4.0
2.2
4.2
2.3
4.5
2.0
4.0
2.2
4.1
2.2
4.5
3.2
1.6
0.7
1.6
0.9
1.6
0.7
1.6
0.5
2.1
0.7
1.6
0.7
1.6
0.7
2.1
0.5
1.6
0.8
1.6
0.7
1.6
0.7
1.6
0.7
1.4
0.5
4.0
2.2
4.0
2.6
3.9
2.4
3.9
2.2
4.8
2.5
4.0
2.4
4.0
2.4
4.3
2.2
4.5
2.5
4.8
2.2
4.3
2.4
4.4
2.4
4.8
3.4
ns
S0,S3
S0,S3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0,A2,A3,Cn
A0,A2,A3,Cn
A0,A2,A3,Cn
A0,A2,A3,Cn
S3,Cn
S3,Cn
S0,A1
S0,A1
S3,Cn
S3,Cn
S3,Cn
S3,Cn
—
—
A1,B1
A1,B1
A3,B3
A3,B3
A3,B3
A3,B3
A3,B3
A3,B3
Logic high level (+1.11 Vdc) applied to pins listed. All other
input pins are left floating or tied to +0.31 Vdc.
VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 Vdc
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