參數(shù)資料
型號(hào)： MC10H181P
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 4-Bit Arithmetic Logic Unit/Function Generator
中文描述： 10H SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDIP24
封裝： PLASTIC, DIP-24
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 158K
代理商： MC10H181P
SEMICONDUCTOR TECHNICAL DATA
2–275
REV 6
Motorola, Inc. 1996
9/96
The MC10H181 is a high–speed arithmetic logic unit capable of performing
16 logic operations and 16 arithmetic operations on two four–bit words. Full
internal carry is incorporated for ripple through operation.
Arithmetic logic operations are selected by applying the appropriate binary
word to the select inputs (S0 through S3) as indicated in the tables of
arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG)
are provided to allow fast operations on very long words using a second order
look–ahead. The internal carry is enabled by applying a low level voltage to the
mode control input (M).
When used with the MC10H179, full–carry look–ahead, as a second order
look–ahead block, the MC10H181 provides high–speed arithmetic operations
on very long words.
This 10H part is a functional/pinout duplication of the standard MECL 10K
family part with 100% improvement in propagation delay and no increase in
power supply current.
Improved Noise Margin, 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K – Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current— Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range— Plastic
— Ceramic
–55 to +150
–55 to +165
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
FUNCTION SELECT TABLE
Function Select
S3
S2
Logic Functions
M is High C = D.C.
F
Arithmetic Operation
M is LowF
13
15
17
14
S1
S0
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F = A
F = A + B
F = A + B
F = Logical “1”
F = A
B
F = B
F = A
F = A + B
F = A
B
F = A
F = B
F = A + B
F = Logical “0”
F = A
B
F = A
B
F = A
F = A
F = A plus (A
B)
F = A plus (A
B)
F = A times 2
F = (A + B) plus 0
F = (A + B) plus (A
B)
F = A plus B
F = A plus (A + B)
F = (A + B) plus 0
F = A minus B minus 1
F = (A + B) plus (A
B)
F = A plus (A + B)
F = minus 1 (two’s complement)
F = (A
B) minus 1
F = (A
B) minus 1
F = A minus 1
S0 S1
S2
S3
F0
21
20
18
19
16
11
10
9
23
2
A0
B0
A1
B1
A2
B2
A3
3
F1
B
7
F2
6
F3
B
4
8
B3
M
GG
PG
22
5
Cn
Cn+4
DIP
PIN ASSIGNMENT
VCC1
F0
F1
GG
CN + 4
F3
F2
PG
VCC2
M
CN
A0
B0
B1
A1
S1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
B3
A3
B2
VEE
A2
S2
S0
S3
16
15
14
13
9
10
11
12
L SUFFIX
CERAMIC PACKAGE
CASE 758–02
P SUFFIX
PLASTIC PACKAGE
CASE 724–03
FN SUFFIX
PLCC
CASE 776–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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