參數(shù)資料
型號： MC10H186P
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： Hex D Master-Slave Flip-Flop with Reset
中文描述： 10H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 1/4頁
文件大小： 100K
代理商： MC10H186P
SEMICONDUCTOR TECHNICAL DATA
2–280
REV 5
Motorola, Inc. 1996
3/93
The MC10H186 is a hex D type flip–flop with common reset and clock lines.
This MECL 10H part is a functional/pinout duplication of the standard MECL
10K family part, with 100
%
improvement in clock toggle frequency and
propagation delay and no increase in power–supply current.
Propagation Delay, 1.7 ns Typical
Power Dissipation, 460 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range — Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
—
121
—
110
—
121
mA
Input Current High
Pins 5,6,7,10,11,12
Pin 9
Pin 1
—
—
—
430
670
1250
—
—
—
265
420
765
—
—
—
265
420
765
μ
A
Input Current Low
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
μ
A
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
tpd
tset
thold
tr
tf
ftog
trr
0.7
3.0
0.7
3.0
0.7
3.0
ns
Set–up Time
1.5
—
1.5
—
1.5
—
ns
Hold Time
1.0
—
1.0
—
1.0
—
ns
Rise Time
0.7
2.6
0.7
2.6
0.7
2.6
ns
Fall Time
0.7
2.6
0.7
2.6
0.7
2.6
ns
Toggle Frequency
250
—
250
—
250
—
MHz
Reset Recovery Time
(t1–9+)
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
through a 50–ohm resistor to –2.0 volts.
3.0
—
3.0
—
3.0
—
ns
CLOCKED TRUTH TABLE
DIP
PIN ASSIGNMENT
RESET
Q0
Q1
Q2
D0
D1
D2
VEE
VCC
Q5
Q4
Q3
D5
D4
D3
CLOCK
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
* A clock H is a clock transition from
a low to a high state.
R
L
L
L
H
C
L
H *
H *
L
D
X
L
H
X
Qn+1
Qn
L
H
L
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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