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參數(shù)資料
| 型號(hào)： | MC1066 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Hex Inverter Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CDIP -55 to 125 |
| 中文描述： | 符合ACPI的SMBus溫度傳感器內(nèi)部和外部二極管輸入 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 196K |
| 代理商： | MC1066 |
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MC1066
http://onsemi.com
9
STANDBY MODE
The MC1066 allows the host to put it into a low power (I
DD
= 10
μ
A, max) Standby mode. In this mode, the A/D
converter is halted, and the temperature data registers are
frozen. The SMBus port operates normally. Standby mode
can be enabled with either the STBY input pin or the CHIP
STOP bit in the CONFIG register. The following table
summarizes this operation.
Standby Mode Operation
STBY
Chip Stop Bit
One Shot
Operating
Mode
Standby
0
Don’t Care
Don’t Care
1
0
Don’t Care
Normal
1
1
No
Standby
1
1
Yes
Normal (1 Con-
version Only,
then Standby)
SMBus SLAVE ADDRESS
The two pins ADD1 and ADD0 are tri–state input pins
which determine the 7–bit SMBus slave address of the
MC1066. The address is latched during POR. The allowable
addresses are summarized in the table below.
Address Decode Table
ADD0
ADD1
SMBus Address
0
0
0011 000
0
open (3–state)
0011 001
0
1
0011 010
open (3–state)
0
0101 001
open (3–state)
open (3–state)
0101 010
open (3–state)
1
0101 011
1
0
1001 100
1
open (3–state)
1001 101
1
1
1001 110
SERIAL PORT OPERATION
The Serial Clock input (SCL) and bi–directional data port
(SDA) form a 2–wire bi–directional serial port for
programming and interrogating the MC1066. The following
conventions are used in the bus architecture in the
followingtable. (See SMBus Write/Read Timing Diagram.)
All transfers take place under control of a host, usually a
CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The MC1066
always
operates as a slave. The serial protocol is illustrated
in Figure 3. All data transfers have two phases; all bytes are
transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes a
Read/Write selection bit. Each access must be terminated by
a Stop Condition (STOP). A convention called
Acknowledge
(ACK) confirms receipt of each byte. Note
that SDA can change only during periods when SCL is LOW
(SDA changes while SCL is High are reserved for Start and
Stop conditions.)
MC1066 Serial Bus Conventions
Term
Explanation
Transmitter
The device sending data to the bus.
Receiver
The device receiving data from the bus.
Master
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
Slave
The device addressed by the master.
Start
A unique condition signaling the beginning
of a transfer indicated by SDA falling (High
— Low) while SCL is high.
Stop
A unique condition signaling the end of a
transfer indicated by SDA rising (Low —
High) while SCL is high.
ACK
A receiver acknowledges the receipt of
each byte with this unique condition. The
receiver drives SDA low during SCL high
of the ACK clock–pulse. The Master pro-
vides the clock pulse for the ACK cycle.
Busy
Communication is not possible because
the bus is in use.
When the bus is idle, both SDA and SCL
will remain high.
The state of SDA must remain stable dur-
ing the High period of SCL in order for a
data bit to be considered valid. SDA only
changes state while SCL is low during nor-
mal data transfers (see Start and Stop
conditions).
NOT Busy
Data Valid
Start Condition (START)
The MC1066 continuously monitors the SDA and SCL
lines for a start condition (a High to Low transition of SDA
while SCL is High), and will not respond until this condition
is met. (See SMBus Write/Read Timing Diagram.)
Address Byte
Immediately following the Start Condition, the host must
transmit the address byte to the MC1066. The states of
ADD1 and ADD0 during power–up determine the 7–bit
SMBus address for the MC1066. The 7–bit address
transmitted in the serial bit stream must match for the
MC1066 to respond with an Acknowledge (indicating the
MC1066 is on the bus and ready to accept data). The eighth
bit in the Address Byte is a Read–Write Bit. This bit is 1 for
a read operation or 0 for a write operation.
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