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參數(shù)資料
| 型號： | MC1066 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Hex Inverter Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CDIP -55 to 125 |
| 中文描述： | 符合ACPI的SMBus溫度傳感器內(nèi)部和外部二極管輸入 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 196K |
| 代理商： | MC1066 |
MC1066
http://onsemi.com
2
FUNCTIONAL BLOCK DIAGRAM
Int. Temp
Ext.Temp
Status Byte
Config. Byte
Conv. Rate
Ext. Hi Limit
Ext. Lo Limit
Int. Hi Limit
Int. Lo Limit
CRIT. Limit
Register Set
Modulator
Internal
Sensor
(Diode)
Control
Logic
SMBus
Interface
OS
ALERT/
COMP
STBY
SCL
SDA
ADD 0
ADD 1
CRIT 0
CRIT 1
INT_SEL
D+
D–
PIN DESCRIPTION
Pin No.
Symbol
Type
Description
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6, 10
Input
Address Select Pins (See Address Decode Table)
PIN DESCRIPTION
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1, 5
CRIT[1:0]
Input
CRITICAL Setpoint Bits (See CRITICAL Setpoint Decode Table)
SCL
Input. SMBus serial clock. Clocks data into and out of the
MC1066.
SDA
Bidirectional. Serial data is transferred on the SMBus in
both directions using this pin.
ADD1, ADD0
Inputs. Sets the 7–bit SMBus address. These pins are
“tri–state,” and the SMBus addresses are specified in the
Address Decode Table.
(
NOTE:
The tri–state scheme allows up to nine MC1066s
on a single bus. A match between the MC1066’s address and
the address specified in the serial bit stream must be made
to initiate communication. Many SMBus–compatible
devices with other addresses may share the same 2–wire bus.
These pins are only active at power–on reset, and will latch
into the appropriate states.
ALERT/COMP*
Output, Open Collector, Active Low. The ALERT output
corresponds to the general SMBALERT signal and indicates
an interrupt event. The MC1066 will respond to the standard
SMBus Alert Response Address when ALERT is asserted.
Normally, the ALERT output will be asserted and latched
when any of the following occurs:
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