參數(shù)資料
型號(hào): MC10211L
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: 10K SERIES, DUAL 3-INPUT NOR GATE, CDIP16
封裝: CERAMIC, DIP-16
文件頁(yè)數(shù): 1/3頁(yè)
文件大?。?/td> 49K
代理商: MC10211L
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
423
Publication Order Number:
MC10211/D
MC10211
Dual 3-Input/3-Output NOR
Gate
The MC10211 is designed to drive up to six transmission lines
simul– taneously. The multiple outputs of this device also allow the
wire “OR”–ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10211 particularly useful in
clock distribution applications where minimum clock skew is desired.
PD = 160 mW typ/pkg (No Loads)
tpd = 1.5 ns typ (All Output Loaded)
tr, tf = 1.5 ns typ (20%–80%)
DIP
PIN ASSIGNMENT
VCC1
AOUT
AIN
VEE
VCC2
VCC1
BOUT
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18.
LOGIC DIAGRAM
VCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8
12
11
10
9
13
14
2
7
6
5
3
4
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10211L
CDIP–16
25 Units / Rail
MC10211P
PDIP–16
25 Units / Rail
MC10211FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10211L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10211
AWLYYWW
1
16
MC10211P
AWLYYWW
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