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參數(shù)資料
| 型號(hào)： | MC10231FN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 109K |
| 代理商： | MC10231FN |
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10231/D
MC10231
High Speed Dual Type D
Master-Slave Flip-Flop
The MC10231 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip–flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip–flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip–flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to
master–slave construction.
P
D = 270 mW typ/pkg (No Load)
t
pd = 2 ns typ
t
Tog = 225 MHz typ
t
r, tf = 2.0 ns typ (20%–80%)
R2 13
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
CE2 11
D2 10
S2 12
Q1
Q2
2
3
15
14
CLOCKED TRUTH TABLE
R–S TRUTH TABLE
C
D
Qn+1
R
S
Qn+1
L
X
Qn
L
Qn
H
L
H
L
C = CE + CC. A clock H is a clock
transition from a low to a high state.
H
N.D.
N.D. = Not Defined
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10231L
CDIP–16
25 Units / Rail
MC10231P
PDIP–16
25 Units / Rail
MC10231FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10231L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10231
AWLYYWW
1
16
MC10231P
AWLYYWW
DIP PIN ASSIGNMENT
VCC1
Q1
R1
S1
CE1
D1
VEE
VCC2
Q2
R2
S2
CE2
D2
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10231FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10231FNR2 | 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述: |
| MC10231L | 制造商:ON Semiconductor 功能描述:Flip Flop D-Master-Slave Type Pos-Edge 2-Element 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10231LAGS | 制造商:Motorola Inc 功能描述:10231LAGS |
| MC10231P | 制造商:ON Semiconductor 功能描述:Flip Flop D-Master-Slave Type Pos-Edge 2-Element 16-Pin PDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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