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參數(shù)資料
| 型號： | MC10E337FN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 10E SERIES, 3-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 71K |
| 代理商： | MC10E337FN |
Semiconductor Components Industries, LLC, 2000
October, 2000 – Rev. 3
1
Publication Order Number:
MC10E337/D
MC10E337, MC100E337
5VECL 3Bit Scannable
Registered Bus Transceiver
The MC10E/100E337 is a 3-bit registered bus transceiver with scan.
The bus outputs (BUS0–BUS2) are specified for driving a 25
bus; the
receive outputs (Q0 – Q2) are specified for 50
. The bus outputs feature a
normal HIGH level (VOH) and a cutoff LOW level — when LOW, the
outputs go to – 2.0 V and the output emitter-follower is “off”, presenting a
high impedance to the bus. The bus outputs also feature edge slow-down
capacitors.
Both drive and receive sides feature the same logic, including a loopback
path to hold data. The HOLD/LOAD function is controlled by Transmit
Enable (TEN) and Receive Enable (REN) on the transmit and receive sides
respectively, with a HIGH selecting LOAD. Note that the implementation
of the E337 Receive Enable differs from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan
operation. The asynchronous bus disable (ABUSDIS) disables the bus
immediately for scan mode.
The SYNCEN input is provided for flexibility when re-enabling the bus
after disabling with ABUSDIS, allowing either synchronous or
asynchronous re-enabling. An alternative use is asynchronous-only
operation with ABUSDIS, in which case SYNCEN is tied LOW, or left
open. SYNCEN is implemented as an overriding SET control
(active-LOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is
shifted in through S_IN and output data appears at the Q2 output.
All registers are clocked on the positive transition of CLK. Additional
lead-frame grounding is provided through the Ground pins (GND) which
should be connected to 0V. The GND pins are not electrically connected to
the chip.
The 100 Series contains temperature compensation.
Scannable Version of E336
25 Cutoff Bus Outputs
50 Receiver Outputs
Scannable Registers
Sync. and Async. Bus Enables
Non-inverting Data Path
1500 ps Max. Clock to Bus (Data Transmit)
1000 ps Max. Clock to Q (Data Receive)
Bus Outputs Feature Internal Edge Slow-Down Capacitors
Additional Package Ground Pins
PECL Mode Operating Range: V
CC= 4.2 V to 5.7 V with VEE= 0 V
NECL Mode Operating Range: V
CC= 0 V with VEE= –4.2 V to –5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 1 KV HBM, > 75 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 471 devices
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10E337FN
PLCC–28
37 Units/Rail
MC10E337FNR2
PLCC–28
500 Units/Reel
MC100E337FN
PLCC–28
37 Units/Rail
MC100E337FNR2
PLCC–28
500 Units/Reel
MARKING
DIAGRAMS
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC–28
FN SUFFIX
CASE 776
MC10E337FN
AWLYYWW
MC100E337FN
AWLYYWW
1
28
1
28
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| MC10E404FNR2 | 功能描述:邏輯門 5V ECL Quad Diff RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC10E404FNR2G | 功能描述:邏輯門 5V ECL Quad Diff AND/NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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