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參數(shù)資料
| 型號： | MC100ES8223TC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 447K |
| 代理商： | MC100ES8223TC |
MC100ES8223
MOTOROLA
TIMING SOLUTIONS
6
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100ES8223
The MC100ES8223 uses a thermally enhanced exposed
pad (EP) 64 lead LQFP package. The package is molded so
that the leadframe is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the MC100ES8223 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the
enhanced thermal capabilities of the MC100ES8223. Direct
soldering of the exposed pad to the thermal land will provide
an efficient thermal path. In multilayer board designs, thermal
vias thermally connect the exposed pad to internal copper
planes. Number of vias, spacing, via diameters and land
pattern design depend on the application and the amount of
heat to be removed from the package. A nine thermal via
array, arranged in a 3 x 3 array and using a 1.2 mm pitch in
the center of the thermal land is the absolute minimum
requirement for MC100ES8223 applications on multi-layer
boards. The recommended thermal land design comprises a
5 x 5 thermal via array as shown in Figure 6.
“Recommended thermal land pattern”, providing an efficient
heat removal path.
7
Figure 6. Recommended thermal land pattern
Thermal via array (5x5),
1.2 mm pitch,
0.3 mm diameter
Exposed pad
land pattern
all units mm
7
The via diameter is should be approx. 0.3 mm with 1 oz.
copper via barrel plating. Solder wicking inside the via
resulting in voids during the solder process must be avoided.
If the copper plating does not plug the vias, stencil print
solder paste onto the printed circuit pad. This will supply
enough solder paste to fill those vias and not starve the
solder joints. The attachment process for exposed pad
package is equivalent to standard surface mount packages.
Figure 7. “Recommended solder mask openings” shows a
recommend solder mask opening with respect to the
recommended 5 x 5 thermal via array. Because a large solder
mask opening may result in a poor release, the opening
should be subdivided as shown in Figure 7. For the nominal
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils
should be considered.
Exposed pad
land pattern
7
Figure 7. Recommended solder mask openings
Thermal via array (5x5),
1.2 mm pitch,
0.3 mm diameter
1.0
0.2
all units mm
7
1.0
0.2
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided. For thermal system analysis and junction
temperature calculation the thermal resistance parameters of
the package is provided:
Table 7. Thermal Resistancea
Convection-
LFPM
RTHJAb
°C/W
RTHJAc
°C/W
RTHJCd
°C/W
RTHJBe
°C/W
Natural
57.1
24.9
100
50.0
21.3
200
46.9
20.0
15.8
9.7
400
43.4
18.7
800
38.6
16.9
a. Thermal data pattern with a 3 x 3 thermal via array on
2S2P boards (based on empirical results)
b. Junction to ambient, single layer test board, per
JESD51-6
c. Junction to ambient, four conductor layer test board
(2S2P), per JES51-6
d. Junction to case, per MIL-SPEC 883E, method 1012.1
e. Junction to board, four conductor layer test board (2S2P)
per JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100ES8223 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals. The thermal land should be connected to GND
through connection of internal board layers.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC100ES8223
Low Voltage 1:22 Differential HSTL Clock Fanout Buffer
NETCOM
IDT Low Voltage 1:22 Differential HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8223
6
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