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參數(shù)資料
| 型號： | MC100H644FNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100H SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 167K |
| 代理商： | MC100H644FNR2 |
Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 6
1
Publication Order Number:
MC10H644/D
MC10H644, MC100H644
68030/040 PECL to TTL
Clock Driver
The MC10H/100H644 generates the necessary clocks for the
68030, 68040 and similar microprocessors. The device is functionally
equivalent to the H640, but with fewer outputs in a smaller outline
20lead PLCC package. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of
parttopart skew, withinpart skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H644 also uses differential ECL internally to achieve its
superior skew characteristic.
The H644 includes dividebytwo and dividebyfour stages, both
to achieve the necessary duty cycle and skew to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Symbol).
The 10H version is compatible with MECL 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0 V).
Generates Clocks for 68030/040
Meets 68030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and ECL Power/Ground Pins
Within Device Skew on Similar Paths is 0.5 ns
Asynchronous Reset
Single +5.0 V Supply
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Synchronized Outputs: The device is designed to have the POS
edges of the ÷2 and ÷4 outputs synchronized.
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H644 also contains circuitry to force a stable state of the PECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
Device
Package
Shipping
ORDERING INFORMATION
MC10H644FN
PLCC20
37 Units/Rail
MARKING
DIAGRAM
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
PLCC20
FN SUFFIX
CASE 775
10H644
AWLYYWW
1
MC100H644FN
PLCC20
37 Units/Rail
http://onsemi.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100H646FN | 功能描述:時鐘驅(qū)動器及分配 5V PECL to TTL 1:8 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100H646FNG | 功能描述:時鐘驅(qū)動器及分配 5V PECL to TTL 1:8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100H646FNR2 | 功能描述:時鐘驅(qū)動器及分配 5V PECL to TTL 1:8 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100H646FNR2G | 功能描述:時鐘驅(qū)動器及分配 5V PECL to TTL 1:8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100H680FN | 功能描述:總線收發(fā)器 4-Bit Diff ECL / TTL RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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