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參數(shù)資料
| 型號(hào)： | MC100EP210 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low-Voltage 1:5 Dual Differential ECL/PECL Clock Driver(低壓1:5雙差分ECL/PECL時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 低電壓1:5雙差動(dòng)ECL / PECL的時(shí)鐘驅(qū)動(dòng)器（低壓1:5雙差分ECL / PECL的時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 129K |
| 代理商： | MC100EP210 |
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC100EP210/D
1
REV 1
Motorola, Inc. 2000
06/00
Low–Voltage 1:5 Dual Differential
ECL/PECL Clock Driver
The MC100EP210 is a low skew 1–to–5 dual differential driver,
designed with clock distribution in mind. The input signals can be either
differential or single–ended if the VBB output is used. The signal is
fanned out to 5 identical differential outputs.
150ps Part–to–Part Skew typical
35ps Output–to–Output Skew typical
Differential Design
VBB Output
Voltage and Temperature Compensated Outputs
Low Voltage VEE Range of –2.25 to –3.8V
75k
Input Pulldown Resistors
The EP210 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50
, even if only
one side is being used. In most applications, all ten differential pairs will
be used and therefore terminated. In the case where fewer than ten
pairs are used, it is necessary to terminate at least the output pairs on
the same package side as the pair(s) being used on that side, in order
to maintain minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10–20ps) of the
output(s) being used which, while not being catastrophic to most
designs, will mean a loss of skew margin.
The MC100EP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP210 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP210’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or
Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL,
designers should refer to Motorola Application Note AN1406/D.
The MC100EP210 may be driven single–endedly utilizing the VBB bias output with the CLKA or CLKB input. If a single–ended
signal is to be used, the VBB pin should be connected to the CLKA or CLKB input and bypassed to ground via a 0.01
μ
F capacitor.
The VBB output can only source/sink 0.3mA; therefore, it should be used as a switching reference for the MC100EP210 only.
Part–to–Part Skew specifications are not guaranteed when driving the MC100EP210 single–endedly.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW–VOLTAGE
1:5 DUAL DIFFERENTIAL
ECL/PECL CLOCK DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
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| MC100EP220 | Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver(低壓雙1:10差分ECL/PECL時(shí)鐘驅(qū)動(dòng)器) |
| MC100EP221 | Low-Voltage 1:20 Dual Differential ECL/PECL Clock Driver(低壓1:20雙差分ECL/PECL時(shí)鐘驅(qū)動(dòng)器) |
| MC100EP222 | Low Voltage ECL/PECL 1:15 Clock Driver(低壓ECL/PECL 1:15時(shí)鐘驅(qū)動(dòng)器) |
| MC100EP223 | Low-Voltage 1:22 Differential PECL/HSTL Clock Driver(低壓1:22差分PECL/HSTL時(shí)鐘驅(qū)動(dòng)器) |
| MC100H606FN | Registered Hex TTL/PECL Translator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP210S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210S_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210SFA | 功能描述:時(shí)鐘緩沖器 2.5V 1:5 Dual Diff RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100EP210SFAG | 功能描述:時(shí)鐘緩沖器 2.5V 1:5 Dual Diff LVDS Clock Driver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100EP210SFAR2 | 功能描述:時(shí)鐘緩沖器 2.5V 1:5 Dual Diff RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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