參數(shù)資料
型號(hào): MC100EL56DW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual Differential 2:1 Multiplexer
中文描述: 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 1/4頁
文件大?。?/td> 113K
代理商: MC100EL56DW
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
4/95
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The
MC100EL56 is pin and functionally equivalent to the MC100LVEL56 but
is specified for operation at the standard 100E ECL voltage supply. The
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals. Multiple VBB pins are provided to
ease AC coupling input signals (for more information on AC coupling ECL
signals refer to the interfacing section of the ECLinPS data book
DL140/D).
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE, The D input will bias around VCC/2
forcing the Q output LOW.
Differential Inputs and Outputs
20–Lead SOIC Packaging
440ps Typical Propagation Delays
Separate and Common Select
Supports Both Standard and Low Voltage 100K ECL
Internal Input Pulldowns
>2000V ESD Protection
D0b
Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
D0b
D1a VBB1
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
SEL0
SEL1
VCC
Q1
Q1
VEE
D0a
19
20
2
1
VCC
Q0
VBB0
D1a
D1b
D1b
D0a
C
SEL
H
L
TRUTH TABLE
Data
a
b
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
1
20
PIN NAMES
Function
Input Data a
Input Data b
Individual Select Input
Common Select Input
True Outputs
Inverted Outputs
Pins
D0a–D1a
D0b–D1b
SEL0–SEL1
COM_SEL
Q0–Q1
Q0–Q1
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