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參數(shù)資料
| 型號(hào)： | MC100EL91DW |
| 廠商： | Motorola, Inc. |
| 元件分類： | 電平轉(zhuǎn)換器 |
| 英文描述： | Triple PECL to ECL T ranslator |
| 中文描述： | 三PECL的? ranslator的ECL |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | MC100EL91DW |
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1997
8/97
The MC100LVEL/EL91 is a triple PECL to ECL translator. The
MC100LVEL91 receives low voltage PECL signals and translates them to
differential ECL output signals. The MC100EL91 receives standard
voltage PECL signals and translates them to differential ECL output
signals.
MC100LVEL91 Supports Low Voltage Operation
MC100LVEL91 Has 620ps Typical Propagation Delays
MC100EL91 Supports Standard Voltage Operation
MC100EL91 Has 670ps Typical Propagation Delays
Fully Differential Design
20–lead SOIC Packaging
A VBB output is provided for interfacing with single ended PECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01
μ
F
capacitor. The VBB output is designed to act as the switching reference
for the EL/LVEL91 under single ended input switching conditions, as a
result this pin can only source/sink up to 0.5mA of current.
To accomplish the level translation the EL/LVEL91 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins are connected to the system ground plain. Both VEE and VCC
should be bypassed to ground via 0.01
μ
F capacitors.
Under open input conditions, the D input will be biased at VCC/2 and
the D input will be pulled to GND. This condition will force the Q output to
a low, ensuring stability.
ECL
ECL
ECL
D2
D1
Figure 1. 20–Lead Pinout
(Top View)
and Logic Diagram
D1
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
Q1
Q1
Q2
Q2
VCC
D0
19
20
2
1
VCC
Q0
D0
D2
VCC
VEE
GND
GND
PECL
PECL
PECL
P
P
DW SUFFIX
20–LEAD PLASTIC SOIC WIDE PACKAGE
CASE 751D–04
PIN NAMES
Function
PECL/LVPECL Inputs
ECL/LVECL Outputs
PECL Reference Voltage Output
Pins
Dn
Qn
PECL_VBB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EL91DWG | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V/5V LVPECL/PECL Input to -5V ECL OUT RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100EL91DWR2 | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V/5V LVPECL/PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100EL91DWR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V/5V LVPECL/PECL Input to -5V ECL OUT RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100ELT20D | 功能描述:轉(zhuǎn)換 - 電壓電平 5V TTL to Diff PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100ELT20DG | 功能描述:轉(zhuǎn)換 - 電壓電平 5V TTL to Diff PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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