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參數(shù)資料
| 型號(hào)： | MC100LVEL92DW |
| 廠商： | Motorola, Inc. |
| 元件分類(lèi)： | 電平轉(zhuǎn)換器 |
| 英文描述： | Replaced by TPS2052B : 0.7A, 2.7-5.5V Dual (1In/ 2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC -40 to 85 |
| 中文描述： | 三向的LVPECL PECL的翻譯 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | MC100LVEL92DW |
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 2
Motorola, Inc. 1997
7/97
The MC100LVEL92 is a triple PECL to LVPECL translator. The device
receives standard PECL signals and translates them to differential
LVPECL output signals.
500ps Propagation Delays
Fully Differential Design
20–Lead SOIC Package
5V and 3.3V Supplies Required
>1500V ESD
A PECL VBB output is provided for interfacing single ended PECL
signals at the inputs. If a single ended PECL input is to be used the PECL
VBB output should be connected to the D input and the active signal will
drive the D input. When used the PECL VBB should be bypassed to
ground via a 0.01
μ
f capacitor. The PECL VBB is designed to act as a
switching reference for the MC100LVEL92 under single ended input
conditions, as a result the pin can only source/sink 0.5mA of current.
To accomplish the PECL to LVPECL level translation, the
MC100LVEL92 requires three power rails. The VCC supply is to be
connected to the standard PECL supply, the LVCC supply is to be
connected to the LVPECL supply, and Ground is connected to the system
ground plane. Both the VCC and LVCC should be bypassed to ground
with a 0.01
μ
f capacitor.
Under open input conditions, the D input will be biased at a VCC/2
voltage level and the D input will be pulled to ground. This condition will
force the “Q” output low, ensuring stability.
D2
D1
Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
D1
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
Q1
Q1
Q2
Q2
VCC
D0
19
20
2
1
VCC
Q0
D0
D2
VCC
GND
LVCC
PECL
VBB
LVCC
PECL
VBB
PECL
LVPECL
PECL
LVPECL
PECL
LVPECL
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
1
20
PIN NAMES
Function
PECL Inputs
LVPECL Outputs
PECL Reference Voltage Output
VCC for LVPECL Output
VCC for PECL Inputs
Common Ground Rail
Pins
Dn
Qn
VBB
LVCC
VCC
GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL92DWG | 功能描述:轉(zhuǎn)換 - 電壓電平 5V Triple PECL to LVPECL RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVEL92DWR2 | 功能描述:轉(zhuǎn)換 - 電壓電平 5V Triple PECL RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVEL92DWR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 5V Triple PECL to LVPECL RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVELT20D | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V LVTTL/LVCMOS RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVELT20DG | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V LVTTL/LVCMOS to Diff LVPECL RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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