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| 型號： | MC100E016FNR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 28-PLCC |
| 產(chǎn)品變化通告： | Reactivation Notice 26/Apr/2011 Product Obsolescence 08/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 100E |
| 邏輯類型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 復(fù)位： | 異步 |
| 計(jì)時： | 同步 |
| 計(jì)數(shù)速率： | 900MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MC10E016, MC100E016
http://onsemi.com
8
APPLICATIONS INFORMATION (continued)
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads
the data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.
H
L
H
LLL
H
TC
PE
CE
TCLD
CLK
P7
P6
P4
P3
P2
P1
P0
P5
Q7
Q6
Q4 Q3
Q2
Q1
Q0
Q5
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the E016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
Table 11. Preset Values for Various Divide Ratios
Divide
Ratio
Preset Data Inputs
P7
P6
P5
P4
P3
P2
P1
P0
2
H
L
3
H
HHHH
L
H
4
H
HHHH
L
5
H
HHH
L
H
w
w
112
H
L
H
LLL
L
113
H
L
HHH
H
114
H
L
HHH
L
254
L
LLLL
H
L
255
L
LLLLL
H
256
L
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed multiple E016s can be cascaded in a manner similar
to that already discussed. When E016s are cascaded to build
larger dividers the TCLD pin will no longer provide a means
for loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must
be used for multiple E016 divider chains.
PE
Clock
TC
Load
DIVIDE BY 113
Load
1001 0000
1001 0001
1111 1100
1111 1101
1111 1110
1111 1111
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
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