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參數(shù)資料
| 型號： | MBM29F160BE-55TR |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 16M (2M X 8/1M X 16) BIT |
| 中文描述： | 2M X 8 FLASH 5V PROM, 55 ns, PDSO48 |
| 封裝： | PLASTIC, REVERSE, TSOP1-48 |
| 文件頁數(shù)： | 22/53頁 |
| 文件大?。?/td> | 251K |
| 代理商： | MBM29F160BE-55TR |
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MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
22
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from an erasing sector.
RY/BY
Ready/Busy Pin
The MBM29F160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29F160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
RESET
Hardware Reset Pin
The MBM29F160TE/BE device may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least t
RP
in order to properly reset the internal state machine. Any
operation in the process of being executed will be terminated and the internal state machine will be reset to the
read mode t
READY
after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device
requires an additional t
RH
before it allows read access. When the RESET pin is low, the device will be in the
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F160TE/BE device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
0
to
DQ
15
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored. Refer to
Figures 13 and 14 for the timing diagrams.
Data Protection
The MBM29F160TE/BE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 3.2 V.
相關PDF資料 |
PDF描述 |
|---|---|
| MBM29F160BE-70PFTN | 16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70PFTR | 16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70TN | 16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70TR | 16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-90PFTN | 16M (2M X 8/1M X 16) BIT |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F160BE-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70PFTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70PFTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29F160BE-70TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29F160BE70TNLE1 | 制造商:Fujitsu 功能描述: |
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