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參數(shù)資料
| 型號(hào)： | MBM29F040A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M (512K ×8) BIT Flash Memoery(512K ×8位 5V 電源電壓閃速存儲(chǔ)器) |
| 中文描述： | 4分（為512k × 8）位閃存Memoery（為512k × 8位5V的電源電壓閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 492K |
| 代理商： | MBM29F040A-70 |
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10
MBM29F040A
-70/-90/-12
Byte 0 (A
0
= V
IL
) represents the manufacture's code (Fujitsu = 04H) and byte 1 (A
0
= V
IH
) the device identifier
code (MBM29F040A = A4H). These two bytes are given in the table 3. All identifiers for manufactures and
device will exhibit odd parity with the MSB (DQ
7
) defined as the parity bit. In order to read the proper device
codes when executing the autoselect, A
1
must be V
IL
(See Table 3.)
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched
on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F040A features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 8). The sector protect feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
= 11.5 V) and CE = V
IH
. The sector addresses (A
18
, A
17
and A
16
) should be set to the sector to be protected.
Table 4 defines the sector address for each of the eight (8) individual sectors. Programming of the protection
circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector
addresses must be held constant during the WE pulse. Refer to figures 10 and 15 sector protection waveforms
and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector addresses (A
16
, A
17
and A
18
) while (A
6
, A
1
, A
0
) = (0,
1, 0) will produce a logical “1” code at device output DQ
0
for a protected sector. Otherwise the device will produce
00H for unprotected sector. In this mode, the lower order addresses, except for A
0
, A
1
and A
6
are DON'T CARE.
Address locations with A
1
= V
IL
are reserved for Autoselect manufacturer and device codes.
Table 4 Sector Address Tables
Sector Address
A
18
A
17
A
16
Address Range
SA0
0
0
0
00000H to 0FFFFH
SA1
0
0
1
10000H to 1FFFFH
SA2
0
1
0
20000H to 2FFFFH
SA3
0
1
1
30000H to 3FFFFH
SA4
1
0
0
40000H to 4FFFFH
SA5
1
0
1
50000H to 5FFFFH
SA6
1
1
0
60000H to 6FFFFH
SA7
1
1
1
70000H to 7FFFFH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F040A-90 | 4M (512K ×8) BIT Flash Memoery(512K ×8位 5V 電源電壓閃速存儲(chǔ)器) |
| MBM29F040A | 4M (512K ×8) Bit Flash Memory( 單5V 電源電壓512K ×8位閃速存儲(chǔ)器) |
| MBM29F040C | 4M (512K X 8) BIT |
| MBM29F040C-55 | Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP -40 to 85 |
| MBM29F040C-55PD | 4M (512K X 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F040A-90-X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 4M 512K X 8 BIT |
| MBM29F040C | 制造商:FUJRTSU 功能描述: |
| MBM29F040C-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PD | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY 4M (512K x 8) BIT |
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