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| 型號(hào)： | MB9BF505RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 118/120頁(yè) |
| 文件大小： | 1277K |
| 代理商： | MB9BF505RPMC |
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97
8266D-MCU Wireless-06/12
ATmega128RFA1
Figure 9-36. ECB Mode - Decryption
Block Cipher
Decryption
Key
Plaintext
Ciphertext
Block Cipher
Decryption
Key
Plaintext
Ciphertext
Due to the nature of AES algorithm the initial key to be used when decrypting is not the
same as the one used for encryption. Instead it is the last round key. This last round
key is the content of the key address space stored after running one full encryption
cycle and must be saved for decryption. If the decryption key has not been saved, it has
to be recomputed by first running a dummy encryption (of an arbitrary plain text) using
the original encryption key. Then the resulting round key must be fetched from the key
memory and written back into the key memory as the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of
these standards do not directly encrypt the payload. Instead they protect the payload by
applying a XOR operation between the original payload and the resulting (AES-) cipher
text with a nonce (number used once). As the nonce is the same for encryption and
decryption only ECB encryption is required. Decryption is performed by a XOR
operation between the received cipher text and its own encryption result concluding in
the original plain text payload upon success.
9.8.8.4.2 Cipher Block Chaining (CBC)
In CBC mode the result of a previous AES operation is XOR-combined with the new
incoming vector forming the new plain text to encrypt as shown in the next figure. This
mode is used for the computation of a cryptographic checksum (message integrity
code, MIC).
Figure 9-37. CBC Mode - Encryption
Block Cipher
Encryption
Key
Ciphertext
Block Cipher
Encryption
Plaintext
Ciphertext
Plaintext
Initialization Vector (IV)
Encryption
Key
ECB
mode
CBC
mode
After preparing the AES key and defining the AES operation direction register bit
AES_DIR, the data has to be provided to the AES engine and the CBC operation can
be started.
The first CBC run has to be configured as ECB to process the initial data (plain text
XOR with an initialization vector provided by the application software). All succeeding
AES runs are to be configured as CBC by setting bit AES_MODE = 1 (AES_CTRL
register). Bit AES_DIR (AES_CTRL register) must be set to AES_DIR = 0 to enable
AES encryption. The data to be processed has to be transferred to the AES_STATE
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| MB9BF516TBGL | 32-BIT, FLASH, RISC MICROCONTROLLER, PBGA192 |
| MB9BF517TPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176 |
| MB9BF517SPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144 |
| MB9BF518TPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176 |
| MB9BF516SPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9BF506NABGL-GE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 112BGA 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 112BGA, Controller Family/Series:ARM Cortex-M3, Core |
| MB9BF506NAPMC-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP, Controller Family/Series:ARM Cortex-M3, Core Size:32bit, No. of I/O's:80, Supply Voltage Min:2.7V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:100, Program Memory Size:512KB, , RoHS Compliant: Yes |
| MB9BF506NBBGL-GE1 | 制造商:FUJITSU 功能描述: |
| MB9BF506NBPMC-G-JNE2 | 制造商:FUJITSU 功能描述: |
| MB9BF506NPMC-ESE1 | 制造商:FUJITSU 功能描述: |
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