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| 型號(hào)： | MB9BF505RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 116/120頁(yè) |
| 文件大小： | 1277K |
| 代理商： | MB9BF505RPMC |
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95
8266D-MCU Wireless-06/12
ATmega128RFA1
9.8.8.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before
starting a security operation. The following steps are required:
Table 9-25. AES Engine Configuration Steps
Step
Description
1
Key Setup
Write encryption or decryption key to KEY
buffer
(16 consecutive byte writes to AES_KEY)
2
AES configuration
Select AES mode: ECB or CBC
Select encryption or decryption
Enable the AES Encryption Ready Interrupt
AES_READY
3
Write Data
Write plain text or cipher text to DATA buffer
(16 consecutive byte writes to AES_STATE)
4
Start operation
Start AES operation
5
Wait for AES finished:
1. AES_READY IRQ or
2. polling AES_DONE bit
(register AES_STATUS) or
3. wait for 24 s
Wait until AES encryption/decryption is finished
successfully
6
Read Data
Read cipher text or plain text from DATA buffer
(16 consecutive byte reads from AES_STATE)
Before starting any security operation a 16 Byte key must be written to the security
engine (refer to section "Security Key Setup" on page 96). This can be done by 16
consecutive write accesses to the I/O register AES_KEY. An internal address counter is
incremented automatically with every read/ write operation. An AES encryption/
decryption run resets the internal byte counter. If the key and data buffer has not been
read or written completely (all 16 Bytes), the following encryption/ decryption operation
will finish with an error.
The following step selects either Electronic Code Book (ECB) or Cipher Block Chaining
(CBC) as the AES_MODE. These modes are explained in more detail in section
"Security Operation Modes" on page 96. Encryption or decryption must be further
selected with bit AES_DIR of register AES_CTRL.
If the AES Error or AES Ready IRQ is used, the interrupt must be enabled with bit
AES_IM.
Next the 128-bit plain text or cipher text data has to be provided to the AES hardware
engine. The 16 data bytes must be consecutively written to the AES_STATE register.
The AES_STATE register can be accessed in the same way as the key register (refer to
The encryption or decryption is initiated with bit AES_REQUEST = 1.
The operation takes 24 s and the completed encryption/ decryption is indicated by the
AES_READY IRQ and the AES_DONE bit. The internal byte counter of the key and
data buffer is cleared and the resulting data can be read out.
For additional information about the key and data buffer please refer to section
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9BF506NABGL-GE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 112BGA 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 112BGA, Controller Family/Series:ARM Cortex-M3, Core |
| MB9BF506NAPMC-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP, Controller Family/Series:ARM Cortex-M3, Core Size:32bit, No. of I/O's:80, Supply Voltage Min:2.7V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:100, Program Memory Size:512KB, , RoHS Compliant: Yes |
| MB9BF506NBBGL-GE1 | 制造商:FUJITSU 功能描述: |
| MB9BF506NBPMC-G-JNE2 | 制造商:FUJITSU 功能描述: |
| MB9BF506NPMC-ESE1 | 制造商:FUJITSU 功能描述: |
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