參數(shù)資料
型號： MB9BF504RPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 21/120頁
文件大小： 1277K
代理商： MB9BF504RPMC
117
8266D-MCU Wireless-06/12
ATmega128RFA1
Bit 4 – CCA_ED_DONE_EN - End of ED Measurement Interrupt Enable
Bit 3 – RX_END_EN - RX_END Interrupt Enable
Bit 2 – RX_START_EN - RX_START Interrupt Enable
Bit 1 – PLL_UNLOCK_EN - PLL Unlock Interrupt Enable
Bit 0 – PLL_LOCK_EN - PLL Lock Interrupt Enable
9.12.19 IRQ_STATUS – Transceiver Interrupt Status Register
Bit
7
6
5
4
NA ($14F)
AWAKE
TX_END
AMI
CCA_ED_DONE
IRQ_STATUS
Read/Write
RW
Initial Value
0
Bit
3
2
1
0
NA ($14F)
RX_END
RX_START
PLL_UNLOCK
PLL_LOCK
IRQ_STATUS
Read/Write
RW
Initial Value
0
This register contains the status of the pending interrupt requests. An interrupt is
pending if the associated bit has a value of one. Such a pending interrupts can be
manually cleared by writing a 1 to that register bit. Interrupts are automatically cleared
when the corresponding interrupt service routine is being executed.
Bit 7 – AWAKE - Awake Interrupt Status
Bit 6 – TX_END - TX_END Interrupt Status
Bit 5 – AMI - Address Match Interrupt Status
Bit 4 – CCA_ED_DONE - End of ED Measurement Interrupt Status
Bit 3 – RX_END - RX_END Interrupt Status
Bit 2 – RX_START - RX_START Interrupt Status
Bit 1 – PLL_UNLOCK - PLL Unlock Interrupt Status
Bit 0 – PLL_LOCK - PLL Lock Interrupt Status
9.12.20 VREG_CTRL – Voltage Regulator Control and Status Register
Bit
7
6
5
4
NA ($150)
AVREG_EXT
AVDD_OK
AVREG_TRIM1
AVREG_TRIM0
VREG_CTRL
Read/Write
RW
R
RW
Initial Value
0
Bit
3
2
1
0
NA ($150)
DVREG_EXT
DVDD_OK
DVREG_TRIM1
DVREG_TRIM0
VREG_CTRL
Read/Write
RW
R
RW
Initial Value
0
This register controls the use of the voltage regulators and indicates their status.
Bit 7 – AVREG_EXT - Use External AVDD Regulator
相關(guān)PDF資料
PDF描述
MB9BF505RPMC 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120
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