參數(shù)資料
型號: MB9BF504RPMC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù): 17/120頁
文件大小: 1277K
代理商: MB9BF504RPMC
113
8266D-MCU Wireless-06/12
ATmega128RFA1
9.12.13 CCA_THRES – Transceiver CCA Threshold Setting Register
Bit
7
6
NA ($149)
CCA_CS_THRES3
CCA_CS_THRES2
CCA_THRES
Read/Write
RW
Initial Value
1
Bit
5
4
NA ($149)
CCA_CS_THRES1
CCA_CS_THRES0
CCA_THRES
Read/Write
RW
Initial Value
0
Bit
3
2
NA ($149)
CCA_ED_THRES3
CCA_ED_THRES2
CCA_THRES
Read/Write
RW
Initial Value
0
1
Bit
1
0
NA ($149)
CCA_ED_THRES1
CCA_ED_THRES0
CCA_THRES
Read/Write
RW
Initial Value
1
This register sets the threshold level for the Energy Detection (ED) of the Clear Channel
Assessment (CCA).
Bit 7:4 – CCA_CS_THRES3:0 - CS Threshold Level for CCA Measurement
These bits are reserved for internal use.
Bit 3:0 – CCA_ED_THRES3:0 - ED Threshold Level for CCA Measurement
These bits define the received power threshold of the Energy above threshold
algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES
[dBm]. Any received power above this level is interpreted as a busy channel.
9.12.14 RX_CTRL – Transceiver Receive Control Register
Bit
7
6
5
4
NA ($14A)
Resx7
Resx6
Resx5
Resx4
RX_CTRL
Read/Write
RW
Initial Value
1
0
1
Bit
3
2
1
0
NA ($14A)
PDT_THRES3
PDT_THRES2
PDT_THRES1
PDT_THRES0
RX_CTRL
Read/Write
RW
Initial Value
0
1
The register controls the sensitivity of the Antenna Diversity Mode. Note that in High
Data Rate modes the ACR module will always be disabled.
Bit 7:4 – Resx7:4 - Reserved
Bit 3:0 – PDT_THRES3:0 - Receiver Sensitivity Control
These register bits control the sensitivity of the receiver correlation unit. If the Antenna
Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it
shall be set back to the reset value. Values not listed in the following table are reserved.
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