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參數(shù)資料
| 型號： | MB9BF504RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 117/120頁 |
| 文件大?。?/td> | 1277K |
| 代理商： | MB9BF504RPMC |
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96
8266D-MCU Wireless-06/12
ATmega128RFA1
Notes:
1. Access to the security block is not possible while the radio transceiver is in state
SLEEP.
2. All configurations of the security module, the SRAM content and keys are reset
during SLEEP or RESET states.
9.8.8.3 Security Key Setup
The key is stored in a 16 Byte sequential buffer. To read or write the contents of the
buffer, 16 consecutive read or write operations to the AES_KEY register are required.
A 16-folded read access to registers AES_KEY returns the last round key of the
preceding security operation. This is the key required for the corresponding ECB
decryption operation after an ECB encryption operation. However the initial AES key
written to the security module in advance of an AES run (see step 1 in Table 9-25 on
page 95) is not modified during an AES operation. This initial key is used for the next
AES run although it cannot be read from AES_KEY.
Before accessing the Key Buffer it must be ensured, that the internal address counter is
initialized correctly. This is the cases after Radio Transceiver Reset (see TRXPR –
Transceiver Pin Register on page 173) or a completed AES Encryption/ Decryption
operation. After an interrupted buffer read or write access, Address pointer
reinitialization is recommended by a simple read access to the AES_CTRL register.
Note:
1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing.
The radio transceiver provides this functionality as an additional feature.
9.8.8.4 Security Operation Modes
9.8.8.4.1 Electronic Code Book (ECB)
ECB is the basic operating mode of the security module and is configured by the
AES_CTRL register. The bit AES_MODE = 0 defines the ECB mode and bit AES_DIR
selects the direction to either encryption or decryption. The data to be processed has to
be written to registers AES_STATE.
A security operation can be started by writing the start command AES_REQUEST = 1
(AES_CTRL register).
The ECB encryption operation is illustrated in Figure 9-35 below. Figure 9-36 on page
97 shows the ECB decryption mode which is supported in a similar way.
Figure 9-35. ECB Mode - Encryption
Block Cipher
Encryption
Key
Plaintext
Ciphertext
Block Cipher
Encryption
Plaintext
Ciphertext
Encryption
Key
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB9BF504RPMC-GE1 | 功能描述:IC MCU 32BIT 256KB FLASH 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:FM3 MB9B500 產品培訓模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標準包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 16x12b; D/A 2x12b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| MB9BF506NABGL-GE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 112BGA 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 112BGA, Controller Family/Series:ARM Cortex-M3, Core |
| MB9BF506NAPMC-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP, Controller Family/Series:ARM Cortex-M3, Core Size:32bit, No. of I/O's:80, Supply Voltage Min:2.7V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:100, Program Memory Size:512KB, , RoHS Compliant: Yes |
| MB9BF506NBBGL-GE1 | 制造商:FUJITSU 功能描述: |
| MB9BF506NBPMC-G-JNE2 | 制造商:FUJITSU 功能描述: |
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