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| 型號(hào)： | MB91F467SAPMC-GSE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 61/144頁(yè) |
| 文件大?。?/td> | 5502K |
| 代理商： | MB91F467SAPMC-GSE2 |
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MB91460S Series
DS07-16617-3E
23
6.
Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
MD_3 pin should be connected directly to ground.
7.
Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-
running operation cannot be guaranteed.
8.
Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9.
Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1) The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction:
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due to a
data event or from the emulator menu.
-
D0 and D1 flags are updated in advance.
-
An EIT handling routine (user interrupt/NMI or emulator) is executed.
-
Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
2) The following behavior occurs when an ORCCR, STILM, MOV Ri, PS instruction is executed to enable a
user interrupt or NMI source while that interrupt is in the active state.
-
The PS register is updated in advance.
-
An EIT handling routine (user interrupt/NMI or emulator) is executed.
-
Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in 1).
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