
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
Page 5 of 125
Table of contents
1
Overview........................................................................................................................ 7
1.1
Block Diagram .......................................................................................................... 7
2
Feature List ................................................................................................................... 8
2.1
Overview Table......................................................................................................... 8
2.2
Core Functionality................................................................................................... 10
2.2.1
Memory Map .................................................................................................... 11
2.2.2
FR70 CPU Core............................................................................................... 13
2.2.3
Instruction Cache ............................................................................................. 13
2.2.4
Interrupt Controller ........................................................................................... 14
2.2.5
Internal Data RAM............................................................................................ 14
2.2.6
Internal Program/Data RAM ............................................................................. 14
2.2.7
External Bus Interface...................................................................................... 14
2.2.8
DMA Controller................................................................................................. 15
2.3
Peripheral Function ................................................................................................ 16
2.4
Embedded Program/Data Memory ......................................................................... 21
2.4.1
Flash features .................................................................................................. 21
2.4.2
CPU Mode ....................................................................................................... 22
2.4.2.1
Flash configuration in CPU mode .......................................................................................... 22
2.4.2.2
Flash access timing settings in CPU mode ............................................................................ 24
2.4.2.3
Address mapping from CPU to parallel programming mode.................................................... 25
2.4.3
Parallel flash programming mode..................................................................... 26
2.4.3.1
Flash configuration in parallel flash programming mode ......................................................... 26
2.4.3.2
Pin connections in parallel programming mode ...................................................................... 27
2.4.4
Flash Security .................................................................................................. 28
2.4.4.1
Vector addresses.................................................................................................................. 28
2.4.4.2
Security Vector FSV1............................................................................................................ 28
2.4.4.3
Security Vector FSV2............................................................................................................ 31
2.4.4.4
Register description for Flash Security................................................................................... 32
3
Recommended Settings ............................................................................................. 33
3.1
PLL and Clockgear settings.................................................................................... 33
3.2
Flash interface settings........................................................................................... 34
3.3
Clock Modulator settings ........................................................................................ 35
4
IO Map.......................................................................................................................... 39
5
Interrupt Vector Table................................................................................................101