
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
Page 3 of 125
2007-04-12
Added MB91F466BA/MB91F464BA information
“A Cover” & 1 & 4.1 & 4.2.1 & 4.2.2
Add
“MB91F466BA” and”MB91F464BA
1.1 & 2.1 Add 832KB/416KB FLASH and explanation of FLASH
2.2.1
Add memory map of MB91F466BA/MB91F464BA
2.2.9
Add 832KB/416KB Fash memory map
6
Add Flash area of MB91F466BA/MB91F464BA
2007-04-19
Change of Chapter Constitution and Addition of
“Recommended
Settings
”
Chap1 Overview
(no change)
Chap2 Feature List
(small change in this Chap)
Chap3 Recommended Settings
(addition)
Chap4 IO Map
(Chap6 in a previous Ver.)
Chap5 Interrupt Vector Table
(Chap3 in a previous Ver.)
Chap6 Package and Pin Assignment (Chap4 in a previous Ver.)
Chap7 Electrical Characteristics
(Chap5 in a previous Ver.)
0.23
2007-05-01
Addition of information to be related Flash
(From 2.4.1 to 2.4.4)
0.24
2007-05-30
Added information of specification change about port function.
2.2.7 & 6.2.2 Add
“Limitation”
2.2.7
Add
“WRX1”
6.2.2
Change function of Pin44.
Changed a division point of IO power supply group
6.2.1 & 6.2.2
Added package dimension in
“6.1 Package”
0.25
2007-06-18
Change of initial value in
“4 IO map”
LVSEL
(04C4h) : 00000111 -> 00000101
REGSEL(04CEh) : 00000110 -> 00000100
0.26
2007-07-24
Changed of initial value in
“4 IO map”
PFR00
(0D80h) : 00000000 -> 11111111
PFR01
(0D80h) : 00000000 -> 11111111
PFR02* (0D80h) : 00000000 -> 11111111
PFR03* (0D80h) : 00000000 -> 11111111
PFR04* (0D84h) : 00000000 -> 11111111
PFR05
(0D84h) :
. . 000000 -> . . 111111
PFR06
(0D84h) : 00000000 -> 11111111
PFR07
(0D84h) : 00000000 -> 11111111
PFR08
(0D88h) : 0
. .0 . . .0 -> 1 . .1 . . .1
PFR09
(0D88h) :
. . . . . . 00 -> . . . . . . 11
PFR10
(0D88h) :
. . . . . . . 0 -> . . . . . . . 1
* PFR02, PFR03, and PFR04 changed only the description.
Because it is a part that IO doesn't have.
0.27
2007-09-05
# 2.1 Changed “Core” and “Resource” frequency.
0Core frequency 80 MHz / 100 MHz -> 96 MHz
0Resource frequency 40 MHz / 50 MHz -> 48 MHz
# 2.2.2 Changed maximum operating frequency and PLL clock
multiplier method.
0Core clock =
“80 MHz /100 MHz” -> “96 MHz”
0multiplied by 20 -> multiplied by 24