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參數(shù)資料
| 型號： | MB91F355APMT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 2/112頁 |
| 文件大小： | 1095K |
| 代理商： | MB91F355APMT |
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MB91350A Series
10
(Continued)
Pin no.
Pin name
Circuit
type
Description
133
SCK5
D
Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is
using the external shift clock mode, or serial I/O5 clock output function is en-
abled.
PG5
General purpose input/output port. This function is enabled when serial I/O5 is
not using the external shift clock mode with the serial I/O5 clock output function
disabled.
134
NMI
H
NMI (Non Maskable Interrupt) input
135
X1A
B
Output clock cycle time. Sub clock
137
X0A
B
Input clock cycle time. Sub clock
138 to
140
MD2 to
MD0
H, J
2 to 0Mode Pins. The levels applied to these pins set the basic operating mode.
Connect VCC or VSS.
Input circuit configuration:
The production model (masked-ROM model) is type H.
The FLASH ROM model is type J.
141
X0
A
Input clock cycle time. Main clock
143
X1
A
Output clock cycle time. Main clock
144
INIT
I
External reset input
147
DREQ2
C
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
tentionally turned on.
PC0
General purpose input/output port.
148
DACK2
C
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
PC1
General purpose input/output port. This function is enabled when the transfer re-
quest acceptance output for DMA is enabled.
149
DEOP2
C
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DSTP2
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
PC2
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
150
DREQ0
C
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
tentionally turned on.
PB0
General purpose input/output port.
151
DACK0
C
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
PB1
General purpose input/output port. This function is enabled when the transfer re-
quest acceptance output for DMA is disabled.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB91F355APMT-002 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F355APMT-GE1 | 制造商:FUJITSU 功能描述:IC 16BIT MCU 5V SMD LQFP176 |
| MB91F356B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F356BPMT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F357B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
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