參數(shù)資料
型號(hào): MB91F133PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 85/123頁
文件大小: 1331K
代理商: MB91F133PMT2
MB91133/MB91F133
64
7.
External Interruption
The external interruption control area is the block that controls the external interruption requests input in INT0
to INT23. The level of request to be detected can be selected from “H”, “L”, “Rising edge” or “ Falling edge”.
Block diagram
Register List
24
R-BUS
Interruption permission register
Gate
Interruption
requests
Factor F/F
Edge detection circuit
Interruption factor register
Request level setting register
24
48
24
INT0 to INT23
External interruption permission register (ENIR)
External interruption factor register (EIRR)
Request level setting register (ELVR)
There are three sets of the above registers (for 8 channels) for a total of 24 channels.
bit
15
14
13
12
11
10
9
8
ER6
ER7
ER5
ER4
ER3
ER2
ER1
ER0
15
14
13
12
11
10
9
8
ER6
ER7
ER5
ER4
ER3
ER2
ER1
ER0
76
5
4
3
2
1
0
LA3
LB3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LA7
LB7
LB6
LA6
LB5
LA5
LB4
LA4
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