參數(shù)資料
型號: MB91F133PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 57/123頁
文件大?。?/td> 1331K
代理商: MB91F133PMT2
MB91133/MB91F133
39
s PERIPHERAL RESOURCES
1.
Bus Interface
The bus interface controls the interface with external memory and external I/O.
Bus Interface Characteristics
24-bit (16 MB) address output
16/8-bit bus width can be set.
Insertion of programmable “automatic memory wait” (maximum of 7 cycles)
Supports “l(fā)ittle endian” mode
Unused addresses / data pins can be used as I/O ports.
Clock doubled should be used if the external bus exceeds 25 MHz. Bus speed is 1/2 of the CPU speed.
Areas
A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be
randomly arranged per 64 KB at least using area selection registers (ASR1 to ASR 5) and area mask registers
(AMR1 to AMR 5) in an area of 4 GB. The area 0 is allocated to space outside the area specified by ASR1 to
ASR5. External areas other than 00010000H to 0005FFFFH are deemed area 0 on resetting.
There is no chip selection output pin so no setting is required. Setting it has no effect on usage.
Figure 4.1-1 shows an example in which areas 1 to 5 are arranged from 00100000H to 0014FFFFH in 64 KB
units. Also, Figure 4.1-2 shows an example in which area 1 is arranged as 00000000H to 0007FFFFH in 512
KB and areas 2 to 5 are arranged as 00100000H to 004FFFFFH in 1-MB units.
00000000H
00080000H
000FFFFFH
001FFFFFH
002FFFFFH
003FFFFFH
004FFFFFH
00080000H
000FFFFFH
0010FFFFH
0011FFFFH
0012FFFFH
0013FFFFH
0014FFFFH
CS0 (1 Mbyte)
CS1 (512 K)
CS0 (512 K)
CS2 (1 Mbyte)
CS3 (1 Mbyte)
CS4 (1 Mbyte)
CS5 (1 Mbyte)
CS0
CS1 (64 Kbyte)
CS2 (64 Kbyte)
CS3 (64 Kbyte)
CS4 (64 Kbyte)
CS5 (64 Kbyte)
Figure 4.1-1
Area Arrangement Example 1
Figure 4.1-2
Area Arrangement Example 2
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