
MB91460 Series
14
DS07-16602-2E
Mode pins (MD0 to MD3)
When using mode pins, connect them directly to VCC pin or VSS pin. To prevent the device from entering test
mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and VCC pin or
VSS pin on the printed circuit board as possible and connect them with low impedance.
Power-on sequences for 3.3 V and 5 V
Immediately after power-on, keep “L” level input to the INIT pin for the oscillation stabilization wait time (8 ms)
to ensure the oscillation stabilization wait time for the oscillator circuit.
There is no power-on sequences.
When executing a reset cancellation (changing INIT pin from “L” level to “H” level), be sure to execute it while
3 V and 5 V power supplies are stable.
Caution on operations during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
External bus setting
This model guarantees the maximum frequency of 40 MHz for the external bus clock SYSCLK.
Setting the base clock frequency to 80 MHz without changing the initial value of DIVR1 (external bus base clock
division setting register) sets the external bus frequency also to 80 MHz. Before changing the base clock
frequency, set SYSCLK not exceeding 40 MHz.
Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC standard.
Notes on PS register
Since some instructions process the PS register in advance, the following exceptional operations may cause a
break in the interrupt process routine or an update of display contents of the flag in the PS register when the
debugger is being used. In either case, as the device is designed to carry out reprocessing correctly upon
returning from such an EIT event, it performs operations before and after the EIT as specified.
1) The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S
instruction accepts a user interrupt/NMI, executes a step, or breaks in response to a data event or emulator
menu.
-D0 and D1 flags are updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
2) The following operations are performed when each instruction of OR CCR, ST ILM, MOV Ri and PS is
executed to enable interrupts while a user interrupt/NMI source has been occurring.
-The PS register is updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as that in 1).