參數(shù)資料
型號: MB91354APMT
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 50 MHz, RISC MICROCONTROLLER, PQFP176
封裝: 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù): 66/140頁
文件大?。?/td> 3803K
代理商: MB91354APMT
MB91350A Series
DS07-16503-5E
31
2.
Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. A
32-bit
16-bit bus converter is connected to the 32-bit bus (F-bus), providing an interface between the CPU
and peripheral resources. A Harvard
Princeton bus converter is connected to both the I-bus and D-bus,
providing an interface between the CPU and the bus controller.
FR CPU
Data
RAM
32-bit
16-bit
bus converter
Harvard
Princeton
bus
converter
D-bus
I-bus
D address
I address
External address
External data
D data
Address
Data
16
24
32
I data
R-bus
F-bus
Peripheral resources
Internal I/O
bus controller
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