參數(shù)資料
型號: MB91354APMT
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 50 MHz, RISC MICROCONTROLLER, PQFP176
封裝: 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù): 21/140頁
文件大?。?/td> 3803K
代理商: MB91354APMT
MB91350A Series
DS07-16503-5E
117
(12) I2C Timing
(VCC
= 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS
= DAVS = AVSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : R,C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not extend the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.0 k,
C
= 50 pF*1
0100
0
400
kHz
Hold time (repeated) START condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓→SDA↓↑
tHDDAT
0
3.45*2
00.9*3
s
Data set-up time
SDA
↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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