參數(shù)資料
型號(hào): MB91302APFF-G-001-BNDE1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 53/140頁
文件大小: 2841K
代理商: MB91302APFF-G-001-BNDE1
MB91301 Series
2
DS07-16502-4E
1.
FR CPU
32-bit RISC, load/store architecture, 5-stage pipeline
68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency
(Max)
= 17 MHz)
General purpose registers : 32 bits
×16
16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store
instructions
Easier assembler coding : Register interlock function
Branch instructions with delay slots : Reduced overhead time in branch executions
Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt (PC, PS save) : 6 cycles, 16 priority levels
2.
Bus interface
Operating frequency : Max 68 MHz (when using SDRAM)
Full 24-bit address output (16 Mbytes memory space)
8-bit, 16-bit or 32-bit data input/output
Built-in pre-fetch buffer
Unused data and address pins can be used as general-purpose input/output ports.
Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units.
Supports the following memory interfaces
Asynchronous SRAM, asynchronous ROM/Flash
Page mode ROM/Flash ROM (selectable page size
= 1, 2, 4, or 8)
Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)
SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)
Address/Data multiplex bus (only 8/16-bit width)
Basic bus cycle : 2 cycles
Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory
area.
RDY input for external wait cycles
Endian setting of byte ordering (Big/Little)
CS0 area only for big endian
Prohibition setting of write (only for Read)
Permission/prohibition setting of fetch into built-in cache
Permission/prohibition setting of prefetch function
DMA supports fly-by transfer with independent I/O wait control
External bus arbitration can be used using BRQ and BGRNT.
3.
Built-in memory
4 Kbytes DATA RAM
ROM: 4 Kbytes (MB91302A)
(Continued)
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