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參數(shù)資料
| 型號： | MB91121PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 57/100頁 |
| 文件大小： | 2316K |
| 代理商： | MB91121PFV |
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MB91121 Series
6
DS07-16303-4E
■ PIN DESCRIPTION
Pin no.
Pin name
Circuit type
Function
1
2
3
4
5
6
7
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
F
Bits 16 to 23 for the external address bus.
When not used for the address bus, these pins serve as ports (P60
to P67) .
8
A24
M
Bit 24 for the external address bus
9AVCC
A/D converter VCC power supply
10
AVRH
A/D converter reference voltage (high potential side)
The VCC pin must be applied with voltage equal to or higher than
the voltage at this pin (AVRH) when the AVRH pin is turned on or
off.
11
AVSS/AVRL
A/D converter VSS power supply or reference voltage (low potential
side)
12 to 19
AN0 to AN7
N
[AN0 to AN7] A/D converter analog input. This function is enabled
with the AIC register set for the analog input.
20 to 23
OCPA0/PH4
OCPA1/PH5
OCPA2/PH6
OCPA3/PH7
F
[OCPA0 to OCPA3] PWM timer output. This function is enabled
with the PWM timer output flag set to “Enabled”.
[PH4 to PH7] General-purpose I/O port
25 to 32
INT0/PG0
INT1/PG1
INT2/PG2
INT3/PG3
INT4/PG4/TRG0
INT5/PG5/TRG1
INT6/PG6/TRG2
INT7/PG7/TRG3
F
[INT0 to INT7] External inter-
rupt request input
Since these inputs are used dur-
ing their respective input opera-
tions, the output by the other
function must remain off unless
used intentionally.
[TRG0 to TRG3] PWM timer
external trigger input
[PG0 to PG7] General-purpose I/O port
33
SI0/PF0
F
[SI0] UART0 data input. Since this input is used whenever
UART0 is in input operation, the output by the other function must
remain off unless used intentionally.
[PF0] General-purpose I/O port
35
SO0/PF1
F
[SO0] UART0 data output. This function is enabled with the
UART0 data output flag set to “Enabled”.
[PF1] General-purpose I/O port. This function is enabled with the
UART0 data output flag set to “Disabled”.
36
SC0/PF2
F
[SC0] UART0 clock input/output. The clock output is enabled with
the UART0 clock output flag set to “Enabled”.
[PF2] General-purpose I/O port. This function is enabled with the
UART0 clock output flag set to “Disabled”.
(Continued)
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相關代理商/技術參數(shù) |
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