參數(shù)資料
型號(hào)： MB90P673
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 54/124頁
文件大?。?/td> 2584K
代理商： MB90P673
MB90670/675 Series
54
7. Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter value of the 24-bit free-run timer to the ICU data register (ICDR) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture external pins and ICU data registers (ICDR), enabling
measurements of maximum of four events.
The input capture has four sets of external input pins (ASR0 to ASR3) and ICU registers (ICDR), enabling
measurements of maximum of four events.
A trigger edge direction can be selected from rising/falling/both edges.
The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
24-bit free-run timer to the ICU data register (ICDR).
The input compare conforms to the extended intelligent I/O service (EI
2
OS).
The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.
(1) Register Configuration
ICU control register upper digits (ICC : H)
Address
bit 15
000053
H
Initial value
00000000
B
IRE3
IRE2
IRE1
IRE0
IR3
IR2
IR1
IR0
(ICC : L)
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . .. . . . . . ..
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICU control register lower digits (ICC : L)
Address
bit 1. . . .. . . . . . ..
000052
H
Initial value
00000000
B
EG3B
EG3A
EG2B EG2A
EG1B
EG1A
EG0B EG0A
(ICC : H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICU upper data register 0 to 3 (ICDR0H to ICDR3H)
Address
ICDR0H : 000063
H
ICDR1H : 000067
H
ICDR2H : 00006B
H
ICDR3H : 00006F
H
Initial value
00000000
B
—
—
—
—
—
—
—
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R
R
R
R
R
R
R
R
Address
ICDR0H : 000062
H
ICDR1H : 000066
H
ICDR2H : 00006A
H
ICDR3H : 00006E
H
D23
D22
D21
D20
D19
D18
D17
D16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX
B
ICU lower data register 0 to 3 (ICDR0L to ICDR3L)
Address
ICDR0L : 000061
H
ICDR1L : 000065
H
ICDR2L : 000069
H
ICDR3L : 00006D
H
D15
D14
D13
D12
D11
D10
D9
D8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R
R
R
R
R
R
R
R
Address
ICDR0L : 000060
H
ICDR1L : 000064
H
ICDR2L : 000068
H
ICDR3L : 00006C
H
D7
D6
D5
D4
D3
D2
D1
D0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX
B
Initial value
XXXXXXXX
B
R/W : Readable and writable
R : Read only
— : Unused
X : Indeterminate
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