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參數(shù)資料
| 型號(hào)： | MB90P673 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 41/124頁 |
| 文件大小： | 2584K |
| 代理商： | MB90P673 |
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41
MB90670/675 Series
(2) N-ch Open-drain Port
Port 5 and port 9 are general-purpose I/O ports having a combined function as resource input/output. Each pin
can be switched between resource and port bitwise.
Only MB90675 series has port 9.
Operation as output port
When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output
latch value is set to “0”, the output transistor is turned on and the pin status is put into an “L” level output, while
writing “1” turns off the transistor and put the pin in a high-impedance status.
If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.
Reading the PDR register returns the pin value (same as the output latch value in the PDR).
Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather
than the pin value, leaving output latch that is not manipulated unchanged.
Operation as input port
Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a high-
impedance status.
Reading the PDR register returns the pin level (“0” or “1”).
Block diagram of port 5
I
ADER (analog input enable register)
PDR (port data register)
ADER read
ADER write
ADER latch
PDR write
PDR read
Output latch
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control (SPL=1)
To analog input
Pin
Output trigger
RMW
(read-modify-write
instruction)
Block diagram of port 9
I
To resource input
PDR write
PDR read
Output latch
PDR (port data register)
From resource output
Output
trigger
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Pin
RMW
(read-modify-
write instruc-
tion)
Standby control
(SPL=1)
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