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參數(shù)資料
| 型號(hào)： | MB90P673 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 40/124頁(yè) |
| 文件大?。?/td> | 2584K |
| 代理商： | MB90P673 |
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MB90670/675 Series
40
I
PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 to 4, 6, 8, A, and B are general-purpose I/O ports having a combined function as an external bus pin and
a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In
the external bus mode, the ports are configured as external bus pins, and part of pins for port 3 can be configured
as general-purpose I/O port by setting the bus control signal select register (ECSR). Each pin corresponding
to upper 4-bit of the port 2 can be switched between a resource and a port bitwise.
Only MB90675 series has port A and port B.
Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, however, values of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the
DDR register as output after writing output data to the PDR register when configuring the bit used as
input as outputs.
Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
Block diagram
PDR (port data register)
DDR (port direction register)
PDR read
PDR write
DDR write
DDR read
Direction latch
Output latch
I
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control (SPL=1)
P-ch
N-ch
Pin
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