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參數(shù)資料
| 型號(hào)： | MB90P623A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 30/80頁(yè) |
| 文件大?。?/td> | 1304K |
| 代理商： | MB90P623A |
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MB90620A Series
30
3. Extended Serial I/O Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSB-
first or MSB-first data transfer can be selected. The serial I/O port to be used can also be selected.
The following two serial I/O operation modes are available.
Internal shift clock mode: Data transfer is synchronization with the internal clock.
External shift clock mode: Data transfer is synchronization with the clock input from the external pin (SCK1).
By manipulating the general-purpose port that shares the external pin (SCK1),
this mode also enables the data transfer operation to be driven by CPU
instructions.
(1) Register Configuration
(2) Block Diagram
Address:
SMD2
SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
Serial mode control
status register
(SMCS)
Serial data register
(SDR)
15
14
13
12
11
10
9
8
000025
H
bit
Address:
—
—
—
—
MODE
BDS
SOE
SCOE
7
6
5
4
3
2
1
0
000024
H
bit
Address:
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
000026
H
bit
Control circuit
Internal data bus
Shift clock counter
Internal clock
Transfer direction selection
Read
Write
Interrupt
request
SIN1
SOT1
SCK1
SDR (Serial data register)
1
0
2
SMD2
SMD1
SMD0
SIR
SIE
BUSY
STOP
STRT
MODE
BDS
SOE
SCOE
(MSB-first) D0 to D7
D7 to D0 (LSB-first)
Internal data bus
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