參數(shù)資料
型號： MB90F804-201PF-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller CMOS
中文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝： 20 X 14 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 22/88頁
文件大?。?/td> 385K
代理商： MB90F804-201PF-G
MB90800 Series
22
(Continued)
Address
Register
abbreviation
PDCRL0
PDCRH0
PCSRL0
PCSRH0
PDUTL0
PDUTH0
PCNTL0
PCNTH0
PDCRL1
PDCRH1
PCSRL1
PCSRH1
PDUTL1
PDUTH1
PCNTL1
PCNTH1
Register
Read/
Write
Resource name
Initial Value
000070
H
000071
H
000072
H
000073
H
000074
H
000075
H
000076
H
000077
H
000078
H
000079
H
00007A
H
00007B
H
00007C
H
00007D
H
00007E
H
00007F
H
000080
H
to
000095
H
000096
H
000097
H
000098
H
to
00009D
H
00009E
H
00009F
H
0000A0
H
PPG0 down counter register
R
16 bit
PPG0
1 1 1 1 1 1 1 1
B
1 1 1 1 1 1 1 1
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
- - 0 0 0 0 0 0
B
0 0 0 0 0 0 0 -
B
1 1 1 1 1 1 1 1
B
1 1 1 1 1 1 1 1
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
- - 0 0 0 0 0 0
B
0 0 0 0 0 0 0 -
B
PPG0 cycle set register
W
PPG0 duty setting register
W
PPG0 control status register
R/W
PPG1 down counter register
R
16 bit
PPG1
PPG1 cycle set register
W
PPG1 duty setting register
W
PPG1 control status register
R/W
(Reserved)
Prohibited
(Reserved)
Prohibited
PACSR
DIRR
LPMCR
ROM correction control register
Delayed interrupt/release
Low power consumption mode
R/W
R/W
R/W
ROM Correction
Delayed interrupt
Low power
consumption
control circuit
0 0 0 0 0 0 0 0
B
- - - - - - - 0
B
0 0 0 1 1 0 0 0
B
0000A1
H
CKSCR
Clock selector
R/W
1 1 1 1 1 1 0 0
B
0000A2
H
to
0000A7
H
0000A8
H
0000A9
H
Prohibited
WDTC
TBTC
Watchdog control
Time-base timer control register
R/W
R/W
Watchdog timer
Time-base timer
Watch timer
(Sub clock)
XXXXX 1 1 1
B
1 - - 0 0 1 0 0
B
0000AA
H
WTC
Watch timer control register
R/W
1 X0 1 1 0 0 0
B
0000AB
H
to
0000AD
H
Prohibited
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