
MB90800 Series
20
(Continued)
Address
Register
abbreviation
SMR1
SCR1
SIDR1/
SODR1
SSR1
Register
Read/
Write
R/W
R/W
Resource name
Initial Value
000028
H
000029
H
Mode Register ch1
Control register ch1
UART1
0 0 0 0 0 - 0 0
B
0 0 0 0 0 1 0 0
B
00002A
H
Input/output data register ch1
R/W
XXXXXXXX
B
00002B
H
00002C
H
Status register ch1
R/W
0 0 0 0 1 0 0 0
B
Prohibited
00002D
H
CDCR1
Communication prescaler control reg-
ister ch1
R/W
Prescaler 1
0 0 - - 0 0 0 0
B
00002E
H
00002F
H
000030
H
000031
H
000032
H
000033
H
000034
H
000035
H
000036
H
000037
H
000038
H
000039
H
00003A
H
00003B
H
00003C
H
00003D
H
00003E
H
00003F
H
000040
H
to
000043
H
000044
H
000045
H
000046
H
000047
H
000048
H
000049
H
00004A
H
00004B
H
00004C
H
00004D
H
Prohibited
ENIR
EIRR
ELVR
External interrupt enable
External interrupt request
External interrupt level (lower)
R/W
R/W
R/W
External interrupt
- - - - 0 0 0 0
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
Prohibited
ADCS0
ADCS1
ADCR0
ADCR1
A/D control status register (lower)
A/D control status register (upper)
A/D data register (lower)
A/D data register (upper)
R/W
R/W
R
R/W
A/D converter
0 0 - - - - - -
B
0 0 0 0 0 0 0 0
B
XXXXXXXX
B
0 0 1 0 1 XXX
B
Prohibited
ADMR
A/D conversion channel set register
R/W
A/D converter
0 0 0 0 0 0 0 0
B
XXXXXXXX
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 - - 0 0 0 0 0
B
CPCLR
Compare clear register
R/W
16-bit free-run
timer
TCDT
Timer Data register
R/W
TCCSL
TCCSH
Timer control status register (lower)
Timer control status register (upper)
R/W
R/W
Prohibited
IPCP0
Input Capture register 0
R
Input Capture 0/1
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
IPCP1
Input Capture register 1
ICS01
Input capture control status 0/1
R/W
Prohibited
OCCP0
Output Compare register 0
R/W
Output compare 0
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
OCCP1
Output Compare register 1
R/W
Output compare 1