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54
MB90650A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare, and two input capture modules.
Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs
and to measure input pulse widths and external clock periods.
Register configuration
Block diagram
TCDTL : 000066
H
TCDTH : 000067
H
bit 15
bit 0
16-bit free-run timer
Timer data register lower, upper (TCDTL, TCDTH)
TCCS : 000068
H
Timer control status register (TCCS)
IPCP0 : 000060
H
, 61
H
IPCP1 : 000062
H
, 63
H
bit 15
bit 0
16-bit input capture
Input capture register channel 0, channel 1
lower, upper (IPCP0, IPCP1)
ICS0, 1 : 000064
H
Input capture control status register (ICS0, 1)
OCCP0 : 000050
H
, 51
H
OCCP1 : 000052
H
, 53
H
OCCP2 : 000054
H
, 55
H
OCCP3 : 000056
H
, 57
H
bit 15
bit 0
OCS0 : 000058
H
OCS1 : 000059
H
OCS2 : 00005A
H
OCS3 : 00005B
H
16-bit output compare
Compare register channel 0 to channel 3
lower, upper (OCCP0 to OCCP3)
Compare control status register
channel 0 to channel 3 (OCS0 to OCS3)
TCDT
OCCP
OCS
IPCP
TCCS
ICS
16-bit free-run timer
Control logic
16-bit timer
Compare register 0
Compare register 1
Compare register 2
Compare register 3
Capture register 0
Capture register 1
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Input capture 0
TQ
TQ
TQ
TQ
Edge selection
Edge selection
Interrupt
T
OUT0
OUT1
OUT2
OUT3
IN0
IN1
Clear
I