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28
MB90650A Series
(Continued)
Address
Register
Register
name
Read/
write
Resource name
Initial value
7B
H
Counter control register channel 1
CCRH1
R/W
8/16-bit up/down
counter/timer
X0001000
B
7C
H
to 7F
H
80
H
81
H
82
H
83
H
84
H
85
H
to 87
H
88
H
89
H
8A to 9E
H
(Reserved area)
IBSR
IBCR
ICCR
IADR
IDAR
(Reserved area)
DTMC
DTMD
I
2
C bus status register
I
2
C bus control register
I
2
C bus clock control register
I
2
C bus address register
I
2
C bus data register
R
I
2
C interface
00000000
B
00000000
B
––0XXXXX
B
–XXXXXXX
B
XXXXXXXX
B
R/W
R/W
R/W
R/W
DTMF control register
DTMF data register
—
—
—
—
00000000
B
000X0000
B
(Reserved area) (Accessing 90
H
to 9E
H
is prohibited)
Delayed interrupt generation/
release register
Low-power consumption mode
control register
9F
H
DIRR
R/W
Delayed interrupt
generation module
Low-power consumption
mode
Low-power consumption
mode
–––––––0
B
A0
H
LPMCR
R/W
00011000
B
A1
H
Clock selection register
CKSCR
R/W
11111100
B
A2
H
to A4
H
A5
H
(Reserved area)
ARSR
Auto-ready function selection register
External address output control
register
Bus control signal selection register
Watchdog timer control register
Timebase timer control register
Watch timer control register
W
External bus pin control circuit
0011––00
B
A6
H
HACR
W
External bus pin control circuit
00000000
B
A7
H
A8
H
A9
H
AA
H
ECSR
WDTC
TBTC
WTC
(Reserved area)
W
External bus pin control circuit
Watchdog timer
Timebase timer
Watch timer
0000*00–
B
XXXXX111
B
1––00000
B
1X–00000
B
R/W
R/W
R/W
AB
H
to AF
H