參數(shù)資料
型號(hào)： MB90F377
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 96/140頁
文件大小： 650K
代理商： MB90F377
MB90370/375 Series
96
19. Parity generator
The parity generator is a simple circuit that generates odd
/
even parity based on the input data. It consists of a
parity generator data register (PGDR) , an odd
/
even parity generation logic and a parity generator control status
register (PGCSR) .
An 8-bit data can be loaded into PGDR, then the parity generator will generate odd
/
even parity based on the
input data. Either odd or even parity can be generated by setting the PGCSR.
For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “1”, otherwise the parity bit will be set to “0”.
For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “0”, otherwise the parity bit will be set to “1”.
Table shows some examples of odd
/
even parity generation.
Input data
Parity bit (odd parity)
(1) Register configuration of parity generator
Parity bit (even parity)
0000 0000
B
0101 0101
B
1000 0000
B
1010 1011
B
1
1
0
0
0
0
1
1
Parity Generator Data Register
Parity Generator Control Status Register
Bit number
PGDR
Address : 000018
H
Read/write
Initial value
Bit number
PGCSR
Address : 000019
H
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
D6
R/W
X
D7
D5
D4
D3
D2
D1
D0
R/W
0
15
14
13
12
11
10
9
8
R
X
PRTY
PSEL
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