參數(shù)資料
型號: MB90F372PMT-G
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 97/153頁
文件大小: 1573K
代理商: MB90F372PMT-G
MB90370 Series
97
22. DTP/External interrupts
The DTP (Data Transfer Peripheral)/external interrupt circuit is activated by the signal supplied to a DTP/external
interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and
generates external interrupts or activates the extended intelligent I/O service (EI
2
OS).
Features of DTP/External interrupt :
Total 6 external interrupt channels
Two request levels (
H
and
L
) are provided for the intelligent I/O service
Four request levels (rise/fall edge, fall edge,
H
level and
L
level) are provided for external interrupt requests
(1) Register configuration
15
___
14
___
13
12
11
10
9
8
___
___
Address: 000027
H
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DTP/Interrupt Source Register
EIRR
Initial value
Read/write
Bit number
Address: 000026
H
7
6
5
4
3
2
1
0
DTP/Interrupt Enable Register
ENIR
Bit number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
EN3
EN2
EN1
EN0
EN5
ER5
ER4
ER3
ER2
ER1
ER0
EN4
15
14
13
12
11
10
9
8
Address: 000029
H
R/W
0
R/W
0
R/W
0
R/W
0
Request Level Setting Register (Upper)
ELVRH
Initial value
Read/write
Bit number
Address: 000028
H
7
6
5
4
3
2
1
0
Request Level Setting Register (Lower)
ELVRL
Bit number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
LB3
LA3
LB1
LA1
LB0
LA0
LB2
LB5
LA5
LB4
LA4
LA2
___
___
___
___
___
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