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參數(shù)資料
| 型號(hào)： | MB90F372PMT-G |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 133/153頁 |
| 文件大?。?/td> | 1573K |
| 代理商： | MB90F372PMT-G |
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MB90370 Series
133
INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Explanation of Items in Tables of Instructions
Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done the number of cycles suspended as the corrective value to the number of
ordinary execution cycles.
Item
Meaning
Mnemonic
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters:Indicate the bit width within the instruction code.
Indicates the number of bytes.
Indicates the number of cycles.
m: When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the
“
~
”
column.
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers
“
0
”
.
X : Extends with a sign before transferring.
–
: Transfers nothing.
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
–
: No transfer.
Z : Transfers 00
H
to AH.
X : Transfers 00
H
or FF
H
to AH by signing and extending AL.
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
–
: No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
–
: Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
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